Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, D to X)

Test 1: uops

Code:

  fcvtzs x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140432530001000200020001800052254154124832742000200020005415411110011000007331611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454150432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b1e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)6061696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740013005811941725401091010020000100001002000010000500621497914801034001300140130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400130024119417254010010100200001000010020000100005006214979148010340013001301300441300381254763126246301002001000020000202100612000013012213011711202011009910010100100001002100401289878000142212162413140310048100001000010100130039130039130125130135130044
302041300409740013002511941725401001010020000100001002000010000500621497914801034001300130130038130038125476312624930100200100002000020010064200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740013004811941725401001010020000100001002000010000500621497914801034001300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510003100001000010100130039130039130039130039130041
3020413003811611013002311941725401001010020000100001002000010000617621497914805876001300180130038130038125495312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740013002611942225401001010020000100001002000010000500621497914801034001300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740013003811941725401001010020000100001002000010000500621497914801034001300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740013005111941725401001010020000100001002000010000500621497914801034001300130130038130038125478312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510025100001000010100130039130039130039130039130039
302041300389740013002411941725401001010020000100001002000010000500621497914801034001300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510029100001000010100130039130135130039130039130039
302041300389740013002311941725401001010020000100001002000010000500621497914801034001300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130041130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a7a8acbranch mispredict (cb)cfd5d6d9ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000130023119417254001010010200001000010200001000050621497914800140113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000700240127021605112952510000100001000010010130039130389130046130039130039
3002413003897401400013002311941725400101001020000100001020000100005062149791482116911300131300411303591254983126268300102010000200002010000200001300381300381120021109101001010000100100000001127011601112952510000100001000010010130039130039130039130039130039
3002413037797401000013002311941725400101001020000100001120000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127011601112952510000100001000010010130042130039130042130043130455
3002413003897400000013002311941725400101001620000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000930127011601112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127011601112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062151231480002501300131300381300381255003126268300102010000201222010066200001300391300381120021109101001010000100100000000127011602112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127011611112952510000100001000010010130039130039130039130039130039
30024130038974000024013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000030130611602112952510000100001000010010130039130039130039130039130039
3002413003897400000013002411941738400101001020000100001020000100005062149791480002511300131300741300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127011601112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020003100001020000100005062149791480002501300131300381300741254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127011601112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, d8
  fcvtzs x1, d8
  fcvtzs x2, d8
  fcvtzs x3, d8
  fcvtzs x4, d8
  fcvtzs x5, d8
  fcvtzs x6, d8
  fcvtzs x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a7a8a9acc2c5branch mispredict (cb)cdcfd5d6inst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400633000090697252401048010016000410016002050014401324002240041400411997706199921601202001600322001600324004140041118020110099100801001000001021011151330160400388000080000801004004240042400424004240042
16020440041300003003225240104801001600041001608525001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000100011151170160400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199770620173160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004020640042400424004240042
16020440041300002103225240104801001600041001608245001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042403604004240042
1602044004129900003225240104801001600041001600205001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041300002107425240104801001600041001600205001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041300000069725240104801001600041001600205001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
1602044004129900003225240104801001600041001600205001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041300000032252401048010016018810016002050014401324002240041400411997702819992160120200160032200160032400414004111802011009910080100100000100011151170160400388000080000801004004240042400424004240042
1602044004130000123523225240104801001600041001600205001440132400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440043300004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100138502012161113400388000080000800104004240042400424004240042
160024401663000042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502013161111400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100243502013161114400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100129502011161211400388000080000800104004240042400424004240042
160024400413000042225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100234502010161013400388000080000800104004240042400424004240042
160024400412990042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101022222502012161111400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100207502011161214400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100222502013161313400388000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100222502012161013400388000080000800104004240042400424004240042
16002440041299004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100153502013161113400388000080000800104004240042400424004240042