Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, H to W)

Test 1: uops

Code:

  fcvtzs w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454141243253000100020002000180001522541541248327420002000200054154111100110000007321611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414943253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414064253000100020002000180000522541541248327420002000200054154111100110000307311611538100010001000542542542542542
200454141243253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8acc2c5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000130028119417254010010100200001000010020000100005006214979148010340130016013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000140000131012162312952510000100001000010100130039130039130039130039130039
3020413003897400013002311941725401081010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202021009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000130023119542254010010100200031000010020000100005006214979148010341130013013003813003812547616126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012172212952510000100001000010100130039130039130039130039130039
302041300389743564013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038100800013002311941725401001010020000100001002000010000500621497914801034113001301300381301091254763126246301002001000020000200100002000013003813003811202011009910010100100001000210000000000131012162212959510000100001000010100130039130039130039130039130039
302041300419740576013002311941725401001010020000100001002000010000637621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130040130039130039130039
30204130038974000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000012000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400013002311941725401001010020000100001002000010049500621497914801034113001301300381300381254763126246301002001000020000200100002000013003913003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013011413003811202011009910010100100001000010000000000131012162212952510000100001000010100130067130081130039130039130045
3020413004197400013002311941725401001010020000100001002000010000500621497914801034013001331300381300381254763126246301002001000020000200100002000013003813004111202011009910010100100001000010000005450000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03181e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc5branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002024020100002000013003813003811200211091010010100001000100000000012702161112952510000100001000010010130039130039130077130039130039
300241300389740211300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506215445148051230130014013003813003812549831262693001020100002000020100002000013007213004011200211091010010100001000100000000012701161112955910000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130013613004013003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
30024130553978001300231194172540010100102000310000102000010000506215171148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701162112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020102442000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130040130040130039130039
300241300381014001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130069130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831263203001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000112961161112952510000100001000010010130039130048130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, h8
  fcvtzs w1, h8
  fcvtzs w2, h8
  fcvtzs w3, h8
  fcvtzs w4, h8
  fcvtzs w5, h8
  fcvtzs w6, h8
  fcvtzs w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030407080a0b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440041300010100000134252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000111511871699400388000080000801004004240042400424004240042
160204400413000101000001342524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115118916109400388000080000801004004240042400424004240042
160204400413000101000001342524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115118916119400388000080000801004004240042400424004240042
160204400412990101000001342524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115118616611400388000080000801004004240042400424004240042
16020440041300010100000134252401048010016000410016002050014401321400224004140041199770619992160120200160032200160032400414004111802011009910080100100000111511871677400388000080000801004004240042400424004240042
160204400413000101000001342524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115118916910400388000080000801004004240042403684004240042
1602044004130001010000108134252401048010016000410016002050014401321400224004140041199770619992160120200160032200160032400414004111802011009910080100100000111511841677400388000080000801004004240042400424004240042
160204400413000101000001342524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115118916910400388000080000801004004240042400424004240042
160204400412990101000001342524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001003001115118101699400388000080000801004004240042400424004240042
1602044004129901010000012242524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115118101699400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc2cdcfd2icache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400433100105252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000050200071677400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502000101666400388000080000800104004240042400424004240042
160024400413100230252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010030050200071656400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501441768040022400414004119996320021160010201600002016000040041400411180021109108001010000050200081677400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502000111685400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502000101675400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502000111677400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000050200081675400388000080000800104004240042400424004240042
16002440041311042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000050200071677400388000080000800104004240042400424004240042
160024400413110422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100300502000101666400388000080000800104004240042400424004240042