Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, H to X)

Test 1: uops

Code:

  fcvtzs x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03183f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200454150432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131013162212952510000100001000010100130039130039130039130039130039
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012163212952510000100001000010100130039130039130039130039130039
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302051300809740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312625330100200100002000020010000200001300381300381120201100991001010010000100001000500000131014482212952510000100001000010100130039130044130039130039130039
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740001300231194172540100101002000010000100200001000050062152191480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130042130039130039130039
3020413003897400541300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130044130039130039
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740001300231194172540100101002000010000100200001000050062149791480103401300130130039130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)031e3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30024130038974013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701171112952510000100001000010010130039130039130039130039130039
3002413003810081513002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000060012701161112952510000100001000010010130039130039130039130039130039
30024130039974013002311941725400101001020000100001020000100005062149791480002501300131300411300411255003126268300102010000200002010000200001300391300381120021109101001010000101000000418312701161112952510000100001000010010130039130039130039130039130039
30024130038974013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126269300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130258130481130039
300241300381008013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130047
30024130038974013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000720012701161112952510000100001000010010130039130039130039130039130039
30024130038974013002911941725400101001020000100001020000100005062149791480002511300161300381300381254983126268300102010000200002010000200001300381300741120021109101001010000101000000012701161112952510000100001000010010130039130130130039130039130039
30024130038974013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, h8
  fcvtzs x1, h8
  fcvtzs x2, h8
  fcvtzs x3, h8
  fcvtzs x4, h8
  fcvtzs x5, h8
  fcvtzs x6, h8
  fcvtzs x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400413000032252401048010016000410016002050014401320400224044440123199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000055252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000097252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880100080000801004004240042400424004240042
1602044004130000223252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000032252401048010016000410016022050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413001032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000011151171604003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244004229900422524001080010160000101600005014400000400224004140041199960320021160010201600002016000040041400411180021109108001010000502011161174003880000080000800104004240042400424004240042
16002440630321021712524001080010160000101600005014400000400224004140041199960320021160010201600002016000040041400411180021109108001010000502010161164003880000080000800104004240042400424004240042
16002440041300007072524001080010160000101600005014400000400224004140041199960320021160010201600002016000040041400411180021109108001010000502010161174003880000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050201116964003880000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000400224004140041199960320021160010201600002016000040041400411180021109108001010000502011161174003880000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000004002240041400411999603200211600102016000020160000400414004111800211091080010100005020716794003880000080000800104004240042400424004240042
160024400412990042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000050206161174003880000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000140217400414004119996032002116001020160000201600004004140041118002110910800101000050209161174003880000080000800104004240042400424004240042
1600244004129900422524001080010160000101600005014400000400224004140041199960320021160010201600002016000040041400411180021109108001010000502011161474003880000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000400224004140041199960320021160010201600002016000040041400411180022109108001010000502091611104003880000080000800104004240042400424004240042