Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, S to S)

Test 1: uops

Code:

  fcvtzs s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230013261254725100010001000398160030183037303724143289510001000100030373037111001100000073216222629100030383038303830383085
100430372300061254725100010001000398160030183037303724143291410001000100030373037111001100000073216222629100030383038303830383038
1004303723000612547251000100010003981601301830373037241432914100010001000303730371110011000330073216222629100030383038303830383038
100430372310061254725100010001000398160030183084303724143289510001000100030373037111001100000073216222629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100003073216222629100030383038303830383038
100430372300061254725100010001000398160030183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
100430372400061254725100010001000398160030183037303724143289510001000100030373037111001100000073216222629100030383038303830383038
1004303723001261254725100010001000398160030183037303724143289510001000100030373037111001100003073216222629100030383038303830383038
1004303724000251254725100010001000398160130183037303724143289510001000100030373037111001100000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000000126295472510100100100001001000050042771600300183008830037282648287451010020410000200100003008530084211020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500090061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071013311296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003008430037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000204100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000010371011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001141000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233000491295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000002640216222962910000103003830038300383003830038
100243003722500061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000000640216222962910000103003830038300383003830038
1002430037225000347295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000000640216222962910000103003830038300383003830038
100243003722500061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000001230640216222962910000103003830038300383003830038
1002430037225000232295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000640216222962910000103003830038300853008530038
1002430037232000789295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000000640216222962910000103003830038300383003830038
1002430037225000103295472510010101000010100005042771600300183003730037282863287671016220100002010000301333003711100211091010100001002010000661216422962910000103003830038300383003830038
1002430037225000885295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000028580640216222962910000103003830038300383003830038
1002430037225000508295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000000640216222962910000103003830038300383003830038
10024300372250120877295472510010101000010100005042771600300183003730037282863287671001020100002010172300373003711100211091010100001000000000640216422973710000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs s0, s8
  fcvtzs s1, s8
  fcvtzs s2, s8
  fcvtzs s3, s8
  fcvtzs s4, s8
  fcvtzs s5, s8
  fcvtzs s6, s8
  fcvtzs s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058155000006990302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391550000033306952580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391560000000302580108100800081008002050064013202002020039200399977699908012020080032200801362011620039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391610000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391550000000302580108100800081008002051864013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391560000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001001011151180161020036800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132020020200422009099776100168012020080032200800322003920039118020110099100100800001000311151180160020036800001002004020040200402004020040
80204200391550000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391550000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391550000000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accdcfd0d5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050161040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000000502001816016162003680000102004020040200402004020040
800242003915504025800101080000108000050640000020020201732009210013310019800102080000208000020039200391180021109101080000100000005020061606162003680000102004020040200402004020040
8002420039155124025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000010050200161601362003680000102004020040200402004020040
8002420039155040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000502001516216172003680000102004020040200402004020040
800242003916134025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050200161606162003680000102004020040200402004020040
8002420039155068258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000502001616016112003680000102004020040200402004020040
800242003915504025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000000050200161601662003680000102004020040200402004020040
8002420039156040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000502001616016162003680000102004020040200402004020040
80024200391550402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000305020061606162003680000102004020040200402004020040
80024200391550822580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000005020061606132003680000102004020040200402004020040