Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, S to W)

Test 1: uops

Code:

  fcvtzs w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
20045414017025300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541408525300010002000200018000152254154124832742000200020005415411110011000007321612538100010001000542542542542542
2004541404348300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000037321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f203a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2cfd0d5d6dbddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000000001300231194172540100101192000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000001310121602212954210000100001000010100130039130039130384130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000001310121602212952510000100001000010100130039130039130377130048130039
30204130038974000012352001300231194172540100101002000010000100200001000050062151231480194501300131300381300381254763126249301002001000020000200100002000013003813004111202011009910010100100001000010000000001310121602312952510000100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381256073126246301002001000020000200100002000013003813003811202011009910010100100001000010000000001310121602212952510000100001000010100130039130042130039130039130039
302041300389740000000013002311941810740100101002000010000100200001000050062149791480103401300131300381300381254763126249301002001000020000200100002000013003813004351202011009910010100100001000010000040021384121602212952510003100001000010100130039130039130039130039130039
3020413003897400006360001300231194174640100101002000010000100200001000050062150271480114601300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001004010000000001310121602212952510000100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000105200001000050062149791480103401300131300381300381254763126250301002001000020000200100002000013003813003811202011009910010100100001000010000000321310121602212952710000100001000010100130041130040130039130039130039
302041300389740010120011300251194172540148101032000310005101206941000050062149791480103401302931300391300381256193126246301002001000020000200100002000013003813003811202011009910010100100001000210000010001310151602212952910000100001000010100130039130039130040130198130039
302041300411008000000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000001310121702212952510000100001000010100130042130379130039130039130039
3020413003897400000000130023119417110401001010020000100001002000010000500622426514801034013001313003813003812547625126248301002001000020000200100002000013037913003811202011009910010100100001000010000010301310121603412981610000100001000010100130040130049130071130049130043

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acbranch mispredict (cb)cfd0d5d6d9ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000001300241194172540010100102000010000102000010000506214979148000250130013013003813003812552131262683001020100002000020100002000013003813003811200211091010010100001000100000001270021601112952510000100001000010010130039130039130039130039130039
30024130038974000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000001270011601112952510000100001000010010130039130039130039130039130039
300241300389740000024001300231194182540010100102000010000102000010000506214979148000250130062013003813003812549831262683018020100002000020100002000013003813003811200211091010010100001000100002001270011601112952510000100001000010010130039130039130039130039130039
30024130038974000000001300231194192540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000001270041601112959910000100001000010010130039130439130309130039130039
300241300389750000112001300231194172540010100102000010000102000010000506214979148000250130013013003813003912549831262703001020100002000020100002000013003813003811200211091010010100001000100000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974000000001300231194172540010100102000010000102000010000556217283148000250130013013003813003812550131262683001020100002000020100002000013003813003811200211091010010100001000100000001270011601112952510000100001000010010130039130039130039130085130039
30024130039974000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974000000001300251194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000001270011601112952510000100001000010010130039130040130039130075130040
30024130038974000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002013213003813003811200211091010010100001020100001001270011601112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, s8
  fcvtzs w1, s8
  fcvtzs w2, s8
  fcvtzs w3, s8
  fcvtzs w4, s8
  fcvtzs w5, s8
  fcvtzs w6, s8
  fcvtzs w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)030818191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ec? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440064310000600322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997761999216012020016022420016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
16020440041300000006972524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
16020440041300000003225240104801001600041001600205001440132040212400414004119977371999216012020016003220016003240041400411180201100991008010010000191115117116114003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
1602044004131000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
1602044004129900000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016024040064400521180201100991008010010000001115117116114003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000001115117116114003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03081e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8accdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005530000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000005020616244003880000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000005020416444003880000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000005020616244003880000080000800104004240042400424004240042
16002440041299007072524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000005020416244003880000080000800104004240042400424004240042
160024400412990342252400108001016000010160000501440000004002204004140041199963200211600102016000020160000400414004111800211091080010100021005020416444003880000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000004002204004140041199963200211600102016000020160000400414004111800211091080010100020405020616924003880000080000800104004240042400424004240042
160024400413000063252400108001016000010160000501440000004002204004140041199963200211600102016000020160000400414004111800211091080010100020405020216424003880000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000014002204004140041199963200211600102016000020160000400414004111800211091080010100014415020416244003880000080000800104012340042400424004240042
160024400412990042252400108001016000010160000501440000004002204004140041199963200211600102016000020160000400414004111800211091080010100019505046416244003880000080000800104004240042400424004240042
16002440041299004225240010800101600001016000050144000000400220400414004119996320021160010201600002016000040041400411180021109108001010007205020416424003880000080000800104004240042400424004240042