Firestorm: FCVTZS (scalar, integer, S to W) measurements

Code:

  fcvtzs w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	170	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	85	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	1	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	48	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	3	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10119	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	0	2	2	129542	10000	10000	10000	10100	130039	130039	130384	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	0	2	2	129525	10000	10000	10000	10100	130039	130039	130377	130048	130039
30204	130038	974	0	0	0	0	12	352	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6215123	14801945	0	130013	130038	130038	125476	3	126249	30100	200	10000	20000	200	10000	20000	130038	130041	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	0	2	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125607	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	16	0	2	2	129525	10000	10000	10000	10100	130039	130042	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119418	107	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126249	30100	200	10000	20000	200	10000	20000	130038	130043	5	1	20201	100	99	100	10100	10000	100	0	0	10000	0	4	0	0	2	1384	1	2	16	0	2	2	129525	10003	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	636	0	0	0	130023	119417	46	40100	10100	20000	10000	100	20000	10000	500	6215027	14801146	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	4	0	10000	0	0	0	0	0	1310	1	2	16	0	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	105	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126250	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	2	1310	1	2	16	0	2	2	129527	10000	10000	10000	10100	130041	130040	130039	130039	130039
30204	130038	974	0	0	1	0	12	0	0	1	130025	119417	25	40148	10103	20003	10005	101	20694	10000	500	6214979	14801034	0	130293	130039	130038	125619	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	2	10000	0	1	0	0	0	1310	1	5	16	0	2	2	129529	10000	10000	10000	10100	130039	130039	130040	130198	130039
30204	130041	1008	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	2	17	0	2	2	129525	10000	10000	10000	10100	130042	130379	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	110	40100	10100	20000	10000	100	20000	10000	500	6224265	14801034	0	130013	130038	130038	125476	25	126248	30100	200	10000	20000	200	10000	20000	130379	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	3	0	1310	1	2	16	0	3	4	129816	10000	10000	10000	10100	130040	130049	130071	130049	130043

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	0	0	0	130024	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125521	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	2	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	24	0	0	130023	119418	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130062	0	130038	130038	125498	3	126268	30180	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	2	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	130023	119419	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	4	16	0	1	1	129599	10000	10000	10000	10010	130039	130439	130309	130039	130039
30024	130038	975	0	0	0	0	1	12	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130039	125498	3	126270	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	55	6217283	14800025	0	130013	0	130038	130038	125501	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130085	130039
30024	130039	974	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	130025	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130040	130039	130075	130040
30024	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20132	130038	130038	1	1	20021	10	9	10	10010	10000	10	2	0	10000	1	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, s8
  fcvtzs w1, s8
  fcvtzs w2, s8
  fcvtzs w3, s8
  fcvtzs w4, s8
  fcvtzs w5, s8
  fcvtzs w6, s8
  fcvtzs w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40064	310	0	0	0	60	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160224	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	697	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40212	40041	40041	19977	37	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	9	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160240	40064	40052	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40055	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	6	16	2	4	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	16	4	4	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	6	16	2	4	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	707	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	16	2	4	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	3	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	210	0	5020	4	16	4	4	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	204	0	5020	6	16	9	2	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	63	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	204	0	5020	2	16	4	2	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	144	1	5020	4	16	2	4	40038	80000	0	80000	80010	40123	40042	40042	40042	40042
160024	40041	299	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	195	0	5046	4	16	2	4	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	72	0	5020	4	16	4	2	40038	80000	0	80000	80010	40042	40042	40042	40042	40042

FCVTZS (scalar, integer, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations