Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, S to X)

Test 1: uops

Code:

  fcvtzs x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541505725300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414052625300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)031e3f4f5051inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ebld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974393130025119417025401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000300001310131633129525100000100001000010100130039130039130039130039130039
30204130038103793130023119417025401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000001310131633129525100000100001000010100130039130039130039130039130039
30204130038974918130023119417025401001010020000100001002000010000500621497914801034013001513003813003812547631262463010020010062200002001000020000130038130038112020110099100101001000010001000000000001310131633129525100000100001000010100130039130077130039130039130039
302041300389741194130023119417025401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000101310131633129525100000100001000010100130039130039130039130039130039
302041300389741068130023119417025401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000001310131633129525100000100001000010100130039130039130039130040130039
302041300389741152130023119417039401001010020000100001002000010000500621497914801988013001313003813003812547831262463010020010000200002001000020000130038130038112020110099100101001000010001000000600001310131633129613100000100001000010100130039130039130039130039130039
3020413003897445130023119417025401001010020000100001002000010000500621497914801034013001313003813003812547631262923010020010000200002001000020000130038130038112020110099100101001000010001000000000001310141633129525100000100001000010100130041130039130039130039130039
302041300389741098130023119417025401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038212020110099100101001000010001000000300001310131633129525100000100001000010100130039130039130039130039130039
30204130038974834130023119417025401001010020000100001002000010000500621497914801034013001313003813007712548431262463010020010000200002001000020000130038130038112020110099100101001000010001000020000001310131633129525100000100001000010100130039130039130039130039130039
3020413003897327130023119417025401001010020000100001002012310000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000001310131623129525100000100001000010100130039130039130075130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b1e1f3f4f5051inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8acc2c5branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000013002311941702540010100102000010000102000010000506214979148000251130013013003813003812549831262703001020100002000020100002000013003813003811200211091010010100001001000001200012706171112952510000100001000010010130039130039130039130039130039
3002413003897400001300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300431300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400001300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000112701161112952510000100001000010010130039130039130039130039130039
3002513004297400001300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000900012701161112952510003100001000010010130039130039130039130039130039
3002413036597400601300231194130254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000201262010000200001300381300382120022109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400901300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012702161112976210000100001000010010130039130039130042130039130039
3002413003897400001300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100003000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941702540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002013113008413004111200211091010010100001001000001500012701161112952710000100001000010010130039130039130039130039130039
3002413003897400001300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130068130045130039
3002413004797400001300231194170254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000300012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, s8
  fcvtzs x1, s8
  fcvtzs x2, s8
  fcvtzs x3, s8
  fcvtzs x4, s8
  fcvtzs x5, s8
  fcvtzs x6, s8
  fcvtzs x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400413000000053252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511711600400388000080000801004004240042400424004240042
160204400413000000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
160204400413000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
160204400413000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042403644004240042
160204400413000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000015032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002240041400411997736199921601202001600322001600324004140041118020110099100801001000000111511701610400388000080000801004004240042400424004240042
160204400413000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
160204400413000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004035940042400424004240042
160204400412990000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a7a8a9acc2cfd0d5d6dadbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440055300042252400108001016000010160000501440000004002204004140041199960320021160010201600002016000040041400411180021109108001010000000050200141610117400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400220400414004119996032002116001020160000201600004004140041118002110910800101000000005020091600512400388000080000800104004240042400424004240042
16002440041299042252402968001016000010160000501440000004021704004140041199960320021160010201600002016000040041400411180021109108001010000000050200131600611400388009080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400220400414004120024032002116001020160000201600004004140041118002110910800101000000005020091600116400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100000000502001016001112400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414012711800211091080010100000000502001216001112400388000080000800104004240042400424004240042
1600244004130007072524001080010160000101600005014400000040022040041400411999603200211600102016000020160000400414004111800211091080010100000000502001216001210400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000040022040041400411999609200211600102016000020160000400414004111800211091080010100000000502001116001411400388000080000800104004240042400424004240042
16002440041299042252400108001016000010160000501440000004002204004140041199960320021160010201600002016000040041400411180021109108001010000000050200516001210400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400220400414004119996032002116001020160000201600004004140041118002110910800101000000005020010160099400388000080000800104004240042400424004240042