Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (vector, fixed-point, 4S)

Test 1: uops

Code:

  fcvtzs v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037231266125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037242706125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723126125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037231776125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372406125472510001000100039816003018303730372414628951000100010003037303711100110000073216222629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs v0.4s, v0.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000000000346295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633000100001003003830038300383003830038
1020430037233000000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071011651301083800100001003060230658307093070530657
10204307062464013113131716105688792942829210277163101121681195083442960880300183003730085283156429011121162281000020012151306603055915110201100991001001000010000023907007101161129633000100001003003830038300383003830038
102043003723300000000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633000100001003003830038300383003830038
102043003723300000000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633000100001003003830038300383003830038
102043003724400000003061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633000100001003003830038300383003830038
102043003723300000000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633000100001003003830038300383003830038
1020430037233000000000642295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129699000100001003003830038300383003830038
102043003723200000000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000307101161129633000100001003003830038300383003830038
1020430037233000000000536295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633000100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233000156612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037211002110910101000010000640214752229629010000103003830038300383003830038
1002430037241000010329547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003723300006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037233000396129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003723300006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722500006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722400036129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
10024300372250001986129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100306402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs v0.4s, v8.4s, #3
  fcvtzs v1.4s, v8.4s, #3
  fcvtzs v2.4s, v8.4s, #3
  fcvtzs v3.4s, v8.4s, #3
  fcvtzs v4.4s, v8.4s, #3
  fcvtzs v5.4s, v8.4s, #3
  fcvtzs v6.4s, v8.4s, #3
  fcvtzs v7.4s, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200671550123025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
80204200391550123025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000003011151180160020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
8020420039155003025801081008000810080020500640132020020200902009099776100148012020080142200800322003920039118020110099100100800001000021481011151180160020036800001002004020040200402004020040
8020420039155003025803061008000810080020500640132120020200392009399776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
8020420039156003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000011151180160020036800001002004020040200402004020040
8020420039156093025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000010011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e243a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051161000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100014850200616562003680000102004020040200402004020040
800242003915600040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200616462003680000102004020040200402004020040
800242003915500061258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200716782003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200416472003680000102004020040200402004020040
800242003915600040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200516562003680000102004020040200402004020040
800242003915500083258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010001050200816662003680000102004020040200402004020040
800242003915600040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200416642003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200416482003680000102004020040200402004020040
800242003915500061258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000350200516752003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050200516462003680000102004020040200402004020040