Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (vector, fixed-point, 8H)

Test 1: uops

Code:

  fcvtzs v0.8h, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723010325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs v0.8h, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330000000612954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000003000710216112963300100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001803003730085282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
102043003723200000006129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000032060710116112963300100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001803003730037282648287451010020010000200100003003730037111020110099100100100001000004000710116112963300100001003003830038300383003830038
102043003723300000001562954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116112963300100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710116102963300100001003003830038300383003830069
10204300372320000000892954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000001000710116312963300100001003003830038300383022930038
102043003723200001200612951144101001001000810010000500427716013001803003730037282643287451010020010000200100003003730037111020110099100100100001000004030710116112963300100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010253640516552962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640516662962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640516652962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640416562962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001010640616652962910000103003830038300383003830038
100243003722500156295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010480640616552962910000103003830038300383003830038
1002430037225016129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001016640616662962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640616562962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640616652962910000103003830038300383003830038
10024300372250061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010290640416662962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs v0.8h, v8.8h, #3
  fcvtzs v1.8h, v8.8h, #3
  fcvtzs v2.8h, v8.8h, #3
  fcvtzs v3.8h, v8.8h, #3
  fcvtzs v4.8h, v8.8h, #3
  fcvtzs v5.8h, v8.8h, #3
  fcvtzs v6.8h, v8.8h, #3
  fcvtzs v7.8h, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03091e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039156000896258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151184160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006409760200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180160200360800001002004020040200402004020040
8020420039155012030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180160200360800001002004020040200402004020040
802042003915600051258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180160200360800001002004020040200402004020040
8020420039156098830258010810080008100800205006401321200202003920039997769990801202008003220080032201432003911802011009910010080000100000200011151180160200781800001002004020040200402004020040
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100400000011151180160200360800001002004020040200402004020040
802042003915500030258010810080008100801285006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000300011151180160200360800001002004020040200402004020040
802042003915600030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180160200360800001002004020040200402004020040
8020420039156012030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180160200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180160200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015500000692580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000502022169920036080000102004020040200402004020040
800242003915620000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502071681120036080000102004020040200402004020040
80024200391552000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010001050201116101020036080000102004020040200402004020040
80024200391552000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050209167920036080000102004020040200402004020040
80024200391562000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000875020101610720036080000102004020040200402004020040
80024200391552000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010001050205169720036080000102004020040200402004020040
800242003915620000135258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010001050208168720036080000102004020040200402004020040
800242003915520000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100000502081671020036080000102004020040200402004020040
80024200391562000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050207169720036080000102004020040200402004020040
80024200391553000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000050209167920036080000102004020040200402004020040