Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (vector, integer, 2D)

Test 1: uops

Code:

  fcvtzs v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372400103254725100010001000398160030180303730372414328951000100010003037303711100110006073116112629100030383038303830383038
10043037240061254725100010001000398160030180303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230071254725100010001000398160030180303730372414328951000100010003037303711100110001073116112629100030383038303830383038
10043037240061254725100010001000398160030180303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240061254725100010001000398160030180303730372414328951000104310003037303711100110002073116112629100030383038303830383038
10043037240061254725100010001043398160030180303730372414328951000100010003037303711100110001373116112629100030383038303830383038
10043037230061254725100010001000398160030180303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372301261254725100010001000398160030180303730372414328951000100010003037303711100110001073116112629100030383038303830383038
10043037240061254725100010001000398160130180303730372414328951000100010003037303711100110000073116112700100030383038303830383038
10043037230061254725100010001000398160030180303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300121242954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
10204300372320004052954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
10204300372320001312954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010020000071021622296330100001003003830038300383003830038
102043003723300094829547251010010010000100100005004277160030018300373003728264328745101242001017920010008300373003711102011009910010010000100002111171711611296490100001003003830038300383003830038
1020430037232110612954725101001001000010010000500427716003001830037300372827162874010100200100082001000830037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
1020430037233000822954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
10204300372330001242954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
1020430037233000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
10204300372330004602954725101001001000010010000500427716003006430037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038
10204300372330002322954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000071021622296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129547251001010100001010000504277160030018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037232006129547251001010100001010000504277160130018030085301322828632876710010201000020100003003730037111002110910101000010000682216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001012100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216212962910000103003830038300383003830038
1002430037233006129547251001010100001010000504277160130018030037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs v0.2d, v8.2d
  fcvtzs v1.2d, v8.2d
  fcvtzs v2.2d, v8.2d
  fcvtzs v3.2d, v8.2d
  fcvtzs v4.2d, v8.2d
  fcvtzs v5.2d, v8.2d
  fcvtzs v6.2d, v8.2d
  fcvtzs v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039156000000056025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511811612200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511821612200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511811622200360800001002004020040200402004020040
802042003915600000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511821631200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010040000000111511821602200360800001002004020040200402004020040
8020420039156000000033025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511821632200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511831612200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039204021180201100991001008000010000010000111523942821203290800001002039720445204122039920397
8020420454158010869336162036818079810080697102808525116459100203852040520454100492310203809372028054820280972204532045191802011009910010080000100022010353841115185411535203252800001002046020470204552046620463
802042045815911028114970435351758089110380794100809505006467241203872046020454100144210205810442048085320280955201482049810180201100991001008000010000001000111511821622200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915500031725800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020003160005520036080000102004020040200402004020040
80024200391550306325800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020003160005520036080000102004020040200402004020040
800242003915501204025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020003160003320036080000102004020040200402004020040
800242003915600012225800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020005160005420036080000102004020040200402004020040
80024200391560008425800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020003160004420036080000102004020040200402004020040
80024200391550004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001003005020003160007720036080000102004020040200402004020040
80024200391560004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020003160002420036080000102004020040200402004020040
80024200391560004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020004160004420036080000102004020040200402004020040
80024200391550004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020004160004420036080000102004020040200402004020040
80024200391550004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000005020003160003420036080000102004020040200402004020040