Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (vector, integer, 4H)

Test 1: uops

Code:

  fcvtzs v0.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306225472510081000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723010325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724010325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372468425472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs v0.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbbbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000219307101161129633100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000156007101161129633100001003003830038300383003830038
1020430037232061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000150007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100015007101161129633100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001001129007101161129633100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000159007101161129633100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000117007101161129633100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000126007101161129633100001003003830038300383003830038
10204300372330726295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000117007101161129633100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03183f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)dfe0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006404164502962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006405165522962910000103003830038300383003830038
100243003722404322954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006405164502962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006405165402962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716013001830037300842828603287671001020100002010000300373003711100211091010100001006405164502962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006405165402962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006404164502962910000103003830038300383003830038
10024300372240612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006405164502962910000103003830038300383003830038
10024300372330612954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006404165402962910000103003830038300383003830038
100243003722507262954725100101010000101000050427716013001830037300372828603287671001020100002010000300373003711100211091010100001006405165402962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs v0.4h, v8.4h
  fcvtzs v1.4h, v8.4h
  fcvtzs v2.4h, v8.4h
  fcvtzs v3.4h, v8.4h
  fcvtzs v4.4h, v8.4h
  fcvtzs v5.4h, v8.4h
  fcvtzs v6.4h, v8.4h
  fcvtzs v7.4h, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581560000030258010810080008100801205006401321200202003920039997769990801202008003220080032200392008911802011009910010080000100000000011151180016002003600800001002004020040200402004020040
80204200391560000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016022003600800001002004020040200402004020040
80204200391550005713230258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016002003600800001002004020040200402004020040
802042003915500000600258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016002003600800001002004020040200402004020040
80204200391550000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016002003600800001002004020040200402004020040
80204200391550000051258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016002003600800001002004020040200402004020088
802042003915500000555258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016002003600800001002005020050200492004920049
80204200491550000064278011610080016100800285006401961200292004820049997699986801282008003820080038200482004811802011009910010080000100000000021151180016012003600800001002004020040200402004020040
802042003916100000184258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000000011151180016002003600800001002004020040200402004020040
80204200391560000042258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000003011151180016002003600800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfl1i tlb miss demand (d4)d5map dispatch bubble (d6)d9daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511611001522580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109010108000010033005020023169025252003680000102004020040200402004020040
800242003916100040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110901010800001000005020023258014242003680000102004020040200402004020040
800242003915500082258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110901010800001000005020026166025142003680000102004020040200402004020040
8002420039155000402580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109010108000010000050200281610029282003680000102004020040200402004020040
800242003915500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110901010800001010005020024168124142003680000102004020040200402004020040
800242003915509040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110901010800001000005020028168026162003680000102004020040200402004020040
800242003915500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110901010800001000005020027167026172003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110901010800001000005020027166030142003680000102004020040200402004020040
8002420039155012040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110901010800001000005020026166027162003680000102004020040200402004020040
800242003915500040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110901010800001000005020016166027262003680000102004020040200402004020040