Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, D to W)

Test 1: uops

Code:

  fcvtzu w0, d0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541401092530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541415432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454159432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, d0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080a0b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000000000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130070130043112020110099100101001000010010000100000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130136130041112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119419254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125479191262953010020010000200002001000020000130075130040112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130119130039112020110099100101001000010010000000000131012162212952610000100001000010100130039130039130039130039130039
30204130038974000000000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130095130051112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130108130066112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038975000000000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130089130038112020110099100101001000010010000000000131012162312952510000100001000010100130039130039130039130039130039
30204130039975000000900130023119417254010010100200001000010020000100005006214979148012601130013013003813003812552331262463010020010000200002001000020000130038130038112020110099100101001000010010000000100131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc2branch mispredict (cb)cfd0d2icache miss (d3)d5d6d9dadbddinst fetch restart (de)e0? int output thing (e9)eaebecld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300739740000030130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300711120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417314001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001212952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914820526011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119465254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130070130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000200012700001160001112957810000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000102010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160002112952510000000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, d8, #3
  fcvtzu w1, d8, #3
  fcvtzu w2, d8, #3
  fcvtzu w3, d8, #3
  fcvtzu w4, d8, #3
  fcvtzu w5, d8, #3
  fcvtzu w6, d8, #3
  fcvtzu w7, d8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0304080b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400523111000000052252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000030111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000120032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388010280000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000120032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413110000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042401214004240042
160204400413100000000032252401048010016000410016002050014401320400224012840041199770619992160120200160032200160032400414004111802011009910080100100000000111511711600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b1e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accfd0d2d5d6daddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400543100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000291602928400388000080000800104004240042400424004240042
160024400413100047252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000241601628400388000080000800104004240042400424004240042
160024400413110070252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000151602817400388000080000800104004240042400424004240042
1600244004132200538252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000502000291602727400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000281602728400388000080000800104004240042400424004240042
160024400413110042252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000502000271602727400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000251602525400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000271601527400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000502000151602715400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000251602024400388000080000800104004240042400424004240042