Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, D to W)

Test 1: uops

Code:

  fcvtzu w0, d0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541401092530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541415432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454159432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, d0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30204130038974000000000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130070130043112020110099100101001000010010000100000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130136130041112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119419254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125479191262953010020010000200002001000020000130075130040112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130119130039112020110099100101001000010010000000000131012162212952610000100001000010100130039130039130039130039130039
30204130038974000000000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130095130051112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130108130066112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038975000000000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130089130038112020110099100101001000010010000000000131012162312952510000100001000010100130039130039130039130039130039
30204130039975000000900130023119417254010010100200001000010020000100005006214979148012601130013013003813003812552331262463010020010000200002001000020000130038130038112020110099100101001000010010000000100131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
300241300739740000030130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300711120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417314001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001212952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914820526011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119465254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160001112952510000000100001000010010130039130039130070130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000200012700001160001112957810000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000102010000000012700001160001112952510000000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012700001160002112952510000000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, d8, #3
  fcvtzu w1, d8, #3
  fcvtzu w2, d8, #3
  fcvtzu w3, d8, #3
  fcvtzu w4, d8, #3
  fcvtzu w5, d8, #3
  fcvtzu w6, d8, #3
  fcvtzu w7, d8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400523111000000052252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000030111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000120032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388010280000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000120032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413110000000032252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042401214004240042
160204400413100000000032252401048010016000410016002050014401320400224012840041199770619992160120200160032200160032400414004111802011009910080100100000000111511711600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400543100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000291602928400388000080000800104004240042400424004240042
160024400413100047252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000241601628400388000080000800104004240042400424004240042
160024400413110070252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000151602817400388000080000800104004240042400424004240042
1600244004132200538252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000502000291602727400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000281602728400388000080000800104004240042400424004240042
160024400413110042252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000502000271602727400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000251602525400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000271601527400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000104002240041400411999632002116001020160000201600004004140041118002110910800101000502000151602715400388000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000502000251602024400388000080000800104004240042400424004240042