Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, D to X)

Test 1: uops

Code:

  fcvtzu x0, d0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)030818191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414000004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000006425300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414000004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, d0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070a18191e3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003810080000120130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463027220010000200002001000020000130038130038112020110099100101001000010000100000400000131012163212952510000100001000010100130039130039130039130039130039
302041300381007000000130023119425254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080000120130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130067112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000100000131012162212952510000100001000010100130039130039130039130039130039
302041300381008000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130040130039130039
302041300381008000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130044130039130039
302041300381008000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130039130038112020110099100101001000010000100000000010131012162212952510000100001000010100130039130039130039130039130041
302041300381008000000130023119493254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008000090130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000000131013162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a3a6a8a9acmemory order violation (c4)branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003810080000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100001000012701161112952510000100001000010010130039130039130039130039130039
30024130038100800012013002311941725400101001020000100001020000100005062150271480013711300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100001000012701161112952510000100001000010010130039130039130039130039130052
300241300449740000013002911941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100000000012701161112952510000100001000010010130039130040130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010002100020000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000013002711941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001320000100001020000100005062149791480775401300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100000000012701161212952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100021020000100005062156031480105901300130130038130038125498312626830010201000020000201000020000130038130038112002210910100101000010000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062197311480013601300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389730000013002311941725400171001020000100001020115100005062150271480002511300130130038130043125498312626830010201000020000201000020131130038130038112002110910100101000010000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000013002311941725400101001020000100001020000100005062154111480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010000100002000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, d8, #3
  fcvtzu x1, d8, #3
  fcvtzu x2, d8, #3
  fcvtzu x3, d8, #3
  fcvtzu x4, d8, #3
  fcvtzu x5, d8, #3
  fcvtzu x6, d8, #3
  fcvtzu x7, d8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8a9acc2c5branch mispredict (cb)cdcfd5d6dde0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006631000322524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151172160400388000080000801004004240042400424004240042
1602044004131000322524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004131100322524010480100160004100160020500144013214002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004131000322524010480100160004100160020500144013214002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004131102419922524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
160204400413100020642524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170161400388000080000801004004240042400424004240042
160204400413100025742524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000203011151170160400388000080000801004004240042400424004240042
1602044004131000322524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
16020440041311012322524010480100160004100160020500144013204002234004140041199776199921601202001600322001600324004140041118020110099100801001000000011151170160400388000080000801004004240042400424004240042
1602044004131101228434724010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000000211151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b18191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a7a8a9acc2cfd5d6ddinst fetch restart (de)dfe0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531100004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023316333400388000080000800104004240042400424004240042
1600244004132200004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023316233400388000080000800104004240042400424004240042
1600244004131000004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101004000005023416323400388000080000800104004240042400424004240042
1600244004131100007025240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023216233400388000080000800104004240042400424004240042
1600244004131000008425240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023216333400388000080000800104004240042400424004240042
1600244004131100004225240010800101600001016000050144000014011440041400411999632002116001020160000201600004004140041118002110910800101000000005023316333400388000080000800104004240042400424004240042
1600244004131100004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023316333400388000080000800104004240042400424004240042
1600244004131000004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023316233400388009980000800104004240042400424004240042
1600244004131000004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000000005023316333400388000080000800104004240042400424004240042
16002440041310000070725240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000010005023316433400388000080000800104004240042400424004240042