Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, H to W)

Test 1: uops

Code:

  fcvtzu w0, h0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454142743253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414085253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045415043253000100020002000180001522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414050253000100020002000180001522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, h0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03181e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001006420000200100002000013005213003811202011009910010100100001000010000003000131012162212952510000100001000010100130039130039130039130039130039
30205130069974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013004913003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974001300231194142540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013004613003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130042130039130039
302041300381008001300241194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100672000013005713005311202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013008813004611202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013007013003811202011009910010100100001000010000000000131012161212952510000100001000010100130039130039130039130039130039
30204130038974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254993126246301002001000020000200100002000013005313003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013007813004311202011009910010100100001000010000000000131012162212952510000100001000010100130040130039130039130039130039
30204130038974001300231194172540128101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013008813004011202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03081e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc5branch mispredict (cb)cficache miss (d3)d5d6dbddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389730181300231194172540010100102000010000102000010000606215411148000250130067013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000251130057013003813003812549831262693001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148003691130042013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000251130057013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000420001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000251130049013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112959010000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000410000102012010000506215027148000250130022013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130040013003813003812549831262683001020100002000020100002012613007613003811200211090101001010000100010000009021270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506215027148008440130013013003813003812549831262683001020100002000020100002000013003813003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000251130015013003813003812549831262683001020100002000020100002000013013313003811200211090101001010000100010000000001270011601112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, h8, #3
  fcvtzu w1, h8, #3
  fcvtzu w2, h8, #3
  fcvtzu w3, h8, #3
  fcvtzu w4, h8, #3
  fcvtzu w5, h8, #3
  fcvtzu w6, h8, #3
  fcvtzu w7, h8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030a0b191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400653110006032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511721612400388000080000801004004240042400424004240042
160204400413110000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511721621400388000080000801004004240042400424004240042
160204400413100009074252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511721621400388000080000801004004240042400424004240042
1602044004131000200448252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100001000111511711622400388000080000801004004240042400424004240042
160204400413100000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511721622400388000080000801004004240042400424004240042
16020440041310000162032252401048010016041210016002050014401320400223400414004119977619992160120200160032200160032401234004111802011009910080100100001030111511721622400388000080000801004004240042400424004240042
160204400413100000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100001000111511711621400388000080000801004004240042400424004240042
160204400413100000032252401048010016000410016063850014401320400220400414004119977619992160120200160456200160032400414004111802011009910080100100000000111511721621400388000080000801004004240042400424012140200
16020440041310110158832252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511721621400388000080000801004004240042400424004240042
160204400413100000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511721622400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a7a8a9acc2c5cfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400423110072084252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000000050200031643400388000080000800104004240042400424004240042
160024400413110027042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000000050200051645400388000080000800104004240042400424004240042
1600244004131000153176422524001080010160000101600005014400004002240041400411999611200671600102016000020160000400414004111800211091080010100001000050200041633400388000080000800104004240042400424004240042
1600244004131000729042252400108001016000010160000501440000400224014140041199963200211600102016000020160000400414004111800211091080010100001000050200021633400388000080000800104004240042400424004240042
16002440041311003042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100001000050200051634400388000080000800104004240042400424004240042
16002440041310000042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000000050200031644400388000080000800104004240042400424004240042
160024400413100045042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000000050200041653400388000080000800104004240042400424004240042
16002440041311000042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000000050200051644400388000080000800104004240042400424004240042
160024400413110000422524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000000000502011031653400388000080000800104004240042400424004240042
160024400413110042042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000000050200041634400388000080000800104004240042400424004240042