Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, H to X)

Test 1: uops

Code:

  fcvtzu x0, h0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2004541406425300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414184325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541408525300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541406425300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, h0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3020413004397400000013002311941925401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000300131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125479312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162112952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125483312624630100200100002000020410000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130041130039130041130039130039
302041300389740000001300231194172540100101002000010000100200001005050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300409740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300391300471120202100991001010010000100001000000000131012162212955110000100001000010100130039130039130039130039130097
302041300389740000001300631194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130041
302041300389740000001300231194182540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001002210010000173850133712162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000030131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3002413003897400012352013002311943625400101001020000100001020000100005062149791480106301300131300451303761254983126268300102010000200002010000200001300391300381120021109101001010000101000070012701161112952510000100001000010010130039130039130039130039130041
3002413003897400000013002311946325400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000020012721161112952510000100001000010010130039130039130039130103130042
300241300389740003090013002411956625400101001020000100001120000100005062149791480002501300171300381300381256363126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311945725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130104130039
3002413003897400000013002311945525400101001020000100001020000100005062149791480002501300131300381300381255013126268300102010000200002010000200001300381300381120021109101001010000101000003012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311946125400101001020000100001020000100005062149791480002501300131300401300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012721161112952510000100001000010010130039130041130039130419130039
30024130038973000000130023119443254001010014200001000010200001000050621497914800025013001313003813003812549827126270300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130090130039
3002413003897400000013002311945425400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000850012701161112952510000100001000010010130070130039130039130039130039
3002413003897400000013002311947725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130045130039130039130039
30024130038974000300013002311948225400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701163112993210000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, h8, #3
  fcvtzu x1, h8, #3
  fcvtzu x2, h8, #3
  fcvtzu x3, h8, #3
  fcvtzu x4, h8, #3
  fcvtzu x5, h8, #3
  fcvtzu x6, h8, #3
  fcvtzu x7, h8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0map dispatch bubble (d6)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400623000032252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117024400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013200400224004140041199771420038160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
160204400413001032252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320040022400414004119977619992160316200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
1602044004130000610252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
1602044004129900463252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100431115117416400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401321440022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401320440022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117416400388000080000801004004240042400424004240042
160204400412990064252401048010016000410016002050014401320440022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117016400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fst unit uop (a7)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400543000901512524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101002005020031643400388000080000800104004240042400424004240042
160024400412990003562524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020031624400388000080000800104004240042400424004240042
160024400413000001512524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020041624400388000080000800104004240042400424012440042
160024400413000004072524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020041644400388000080000800104004240042400424004240042
160024400413000309422524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020041642400388000080000800104004240042400424004240042
160024400412990002792524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020031634400388000080000800104004240042400424004240042
160024400413000002882524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020041653400388000080000800104004240042400424004240042
160024400412990001072524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020041642400388000080000800104025340197401964021440174
160024401943010106522416492524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041318002110910800101010005020021647401608000080000800104004240042400424004240042
1600244004130000012322524001080010160000101600005014400004035840041400411999632010516022620160000201600004004140041118002110910800101000005020021624400388000080000800104004240042400424004240042