Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, S to S)

Test 1: uops

Code:

  fcvtzu s0, s0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724126125472510001000100039816013018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303731212414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzu s0, s0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723200612954725101001001000010010000500427716013001830037300372826403287451010020010000200100003003730037111020110099100100100001000000071001611296330100001003003830038300383003830038
102043003723300612954725101001001000010010600500427716003001830037300372826403287451010020010000200100003003730037111020110099100100100001000000671011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728264032874510100200100002001000030037300371110201100991001001000010000001271011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728264032874510100200100002001000030037300371110201100991001001000010000008471011611296330100001003003830038300383003830038
102043003723200182529547251010010010000100100005004277160130018300373003728264032874510100200100002001000030037300371110201100991001001000010000006071011611296330100001003003830038300383003830038
10204300372320057829547251010010010000100100005004277160130018300373003728264032874510100200100002001000030037300371110201100991001001000010000440071011611296330100001003003830038300383003830038
10204300372330010329547251010010010000100100005004277160130018300853003728264032874510100200100002001000030037300371110201100991001001000010000400071011611296330100001003003830038300383003830038
1020430037233008929547251010010010000100100005004277160030018300373003728264032874510100200100002001000030037300371110201100991001001000010000350071011611296330100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018300373003728264032874510100200100002001000030037300371110201100991001001000010000410071011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264032874510100200100002001000030037300371110201100991001001000010000370071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accdcfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233061295479610048101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037232061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037233061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037233081295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100100640002162229629010000103003830038300383003830038
1002430037233061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037233061295472510010101000010100005042812160030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037232061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037233061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038
1002430037232061295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103008530038300383003830038
1002430037233961295472510010101000010100005042771600030018300373003728286328767100102010000201000030037300371110021109101010000100000640002162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzu s0, s8, #3
  fcvtzu s1, s8, #3
  fcvtzu s2, s8, #3
  fcvtzu s3, s8, #3
  fcvtzu s4, s8, #3
  fcvtzu s5, s8, #3
  fcvtzu s6, s8, #3
  fcvtzu s7, s8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591550000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801600200360800001002004020040200402004020040
80204200391550000722580108100800881008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000100111511801600200360800001002004020040200402004020040
80204200391550000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801600200365800001002004020040200402004020040
80204200391600000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000003111511801600200360800001002004020040200402004020040
80204200391550090302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801600200360800001002004020040200402004020040
80204200391550000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000003111511801600200360800001002004020040200402004020040
80204200391560000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511811601200360800001002004020040200402004020040
80204200391550000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801600200360800001002004020040200402004020040
80204200391560000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801600200360800001002004020040200402004020040
802042003915500001892580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d5map dispatch bubble (d6)daddfetch restart (de)dfe0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001005024371604432003680000102004020040200402004020040
8002420039150040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001005024351603332003680000102004020040200402004020040
8002420039150040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001005024331602232003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039100113100198001020800002080000200392003911800211091010800001005024331604432003680000102009620040200402004020040
8002420039150040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001005024331602232003680000102004020040200402004020040
80024200391500402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010050242431603232003680000102004020040200402004020040
800242003915001492580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010050242431604232003680000102004020040200402004020040
80024200391500402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010050242441602232003680000102004020040200402004020040
80024200391500402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010050242431603332003680000102004020040200402004020040
80024200391500402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010050242451602332003680000102004020040200402004020040