Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, S to W)

Test 1: uops

Code:

  fcvtzu w0, s0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414048425300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541406625300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000037311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, s0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030809191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc2cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413004197400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000001300231198631064013610100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002021000020000130038130038112020110099100101001000010010000300131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119422254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417354010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119418254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130077130039130039
3020413003897400000130023119438254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010063200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000131012162212952510000100001000010100130039130039130039130045130042
3020513007797400000130023119419254010010100200001000010020000100005006215027148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000400131012162212952510000100001000010100130039130042130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100100002270131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)6061696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003810080000924552113002311941825400191001920024100031020000100005062149791480002500130013013061413020312598331268253017220100002012320103072072513003813004011200211091010010100001000100000030127001162212959210000100001000010010130041130042130039130039130039
300241300381008000000013002311941725400101001020000100001020000100005062149791480002500130013013003813003812549831263633001020100002000020100002000013003813003811200211091010010100001000100000000127001161212952510000100001000010010130039130039130039130039130039
300241300381008000000013002311941725400101001020000100001020000100005062149791480013610130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127001161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002411941725400101001020000100001020000100005062149791480002510130013013003813003812549831263483001020100002000020100002000013003813003811200211091010010100001000100000000127001161112952510000100001000010010130039130039130039130039130039
300241300381008000000013002311941725400101001020000100001020000100005062149791480002500130013313003813003812550331263143001020100002000020100002000013003813003811200211091010010100001000100000000127001161112952510000100001000010010130039130103130043130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002500130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127001161112952510000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020113100005062149791480002500130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127001161112952510000100001000010010130040130039130039130039130039
3002413003897400007200013002311941725400101001020000100001020000100005062149791480002500130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100001000127001161112957010000100001000010010130039130075130065130039130039
300241301991046000000013002311941725400101001020000100001020000100005062149791480002500130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127001161112952510000100001000010010130039130039130039130039130039
30024130038974000014160013002311941725400101001020000100001020000100005062149791480002500130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127002161112958010000100001000010010130046130042130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, s8, #3
  fcvtzu w1, s8, #3
  fcvtzu w2, s8, #3
  fcvtzu w3, s8, #3
  fcvtzu w4, s8, #3
  fcvtzu w5, s8, #3
  fcvtzu w6, s8, #3
  fcvtzu w7, s8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400642990000322524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000300111511711600400388000080000801004004240042400424004240042
16020440041300000010872524010480100160004100160020500144013204002204004140041199776199921601202001600322001600324004140041118020110099100801001000300111511701600400388000080000801004004240042400424004240042
1602044004130000006972524010480100160004100160020500144013214002204004140041199776199921601202001600322001600324004140041118020110099100801001000100111511701610400388000080000801004004240042400424004240042
160204400413000000322524010480100160004100160020500144013214002204004140041199776199921601202001600322001600324004140041118020110099100801001000503111511701600400388000080000801004004240042400424004240042
1602044004132200003225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010004100111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010001000111511701600400388000080000801004004240042400424004240042
160204400413000009322524010480100160004100160020500144013214002204004140041199776199921601202001600322001600324004140041118020110099100801001000009111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132040022040041400411997761999216012020016003220016003240041400411180201100991008010010005015111511701600400388000080000801004004240042400424004240042
1602044004130000007462524010480100160004100160020500144013204002204004140041199776199921601202001604542001600324004140041118020110099100801001000300111511701601400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132140022040201400411997761999216012020016003220016003240041400411180201100991008010010004503111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03070918191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a8a9acbranch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ec? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005530000000042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000000502012161414400388000014880000800104004240042400424004240042
1600244004130000000042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000000502015251594003880000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020151615164003880000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020161611164003880000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020121613154003880000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020131613174003880000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020121615124003880000080000800104004240042400424004240042
16002440041300000000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020151615124003880000080000800104004240042400424004240042
160024400413000000007072524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000005020151614144003880000080000800104004240042400424004240042
16002440041300100024264422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100100005020131613134003880000080000800104004240042400424004240042