Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, D to W)

Test 1: uops

Code:

  fcvtzu w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8acc2cfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414043253000100020002000180001052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
20045414043253000100020002000180000052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
20045414043253000100020002000180000052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
20045414043253000100020002000180001052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
200454140432530001000200020001800010522541541248327420002000200054154111100110000014730011611538100010001000542542542542542
20045414043253000100020002000180001052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
20045414043253000100020002000180001052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
20045414043253000100020002000180001052254154124832742000200020005415411110011000000730011611538100010001000542542542542542
20045414043253000100020002000180001052254154124832742000200020005415411110011000200730011611538100010001000542542542542542
20045414043253000100020002000180001052254154124832742000200020005415411110011000000730011611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038973000000001300231194192540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510015100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300441300412120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000009001300231194172540100101002000010000100200001000050062149791480103401300130130068130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100016200000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125479312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130040
30204130038974000000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130042130368130042130043130039
30204130038977000000001300231194172540100101002000010000100200001019650062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000003001131012162212952710000100001000010100130041130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080a18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc5cfd5d6d9ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000055201300231194172540010100102000010000102011610000506214979148036540130013130038130038125498312626830010201000020000201006220000130066130038112002110910100101000010001000054000127021602212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262733001020100002000020100002000013003813003811200211091010010100001000100000000127021602212952510000100001000010010130042130039130039130039130039
300241300389740000540130023119417254001010010200001000210200001000050621497914800025013001313003813003812549831262733001020100002000020100002000013003813003811200211091010010100001000100000000127021602212952510000100001000010010130039130039130039130039130039
300241300389730000930130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100001000127021602212952510000100001000010010130039130039130039130039130039
300241300389740000420130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100026000127021602212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262743001020100002000020100002000013003813003811200211091010010100001000100000000127021602212952510000100001000010010130039130039130039130039130039
3002413003897400003301300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010041000850120127021602212952510000100001000010010130039130039130039130039130039
300241300389740000270130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000127021602212952510000100001000010010130039130039130039130039130039
3002413003810080000300130023119417674001010010200001000010200001019650621502714800025013001613003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100001000127021602212952510000100001000010010130216130039130404130039130206
300241301249760012348192130027119417254001010010200001000010200001000050621497914800025013001613003813003812549831262683001020100002000020100002000013004113003811200211091010010100001000100001030127021602212952510000100001000010010130039130042130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, d8
  fcvtzu w1, d8
  fcvtzu w2, d8
  fcvtzu w3, d8
  fcvtzu w4, d8
  fcvtzu w5, d8
  fcvtzu w6, d8
  fcvtzu w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030708090a0b191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440062310100100069725240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100006111511711611400388000080000801004004240042400424004240042
160204400413121002124506025240104801001600041001600205001440132040022400414019920024620125160330200160032200160032400414004111802011009910080100100200111511711611400388000080000801004004240042400424004240042
16020440041311100100032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000012111515211621401028010280000801004012340194400424004240042
1602044004131110010007425240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711611403028000080000801004004240042400424004240042
1602044004131011110003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100006111511711611400388000080000801004004240042400424004240042
1602044004131010010003225240104801001600041001600205001440132140022400414012019977619992160120200160032200160032400414004111802011009910080100100000111511711611400388000080000801004004240042400424004240042
1602044004131110010003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711611400388000080000801004004240042400424004240042
1602044004131010010003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711611400388000080000801004004240042400424004240042
1602044004131010010007425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711614400388000080000801004004240042400424004240042
1602044004131110010003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711611400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8accfd5d6dadbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531004225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000050205160045400388000080000800104004240042400424004240042
1600244004131008625240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000050205160034400388000080000800104004240042400424004240042
1600244004131104225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000050205160035400388000080000800104004240042400424004240042
1600244004132104225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000350205160255400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000050205160356400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101020050204160354400388000080000800104004240042400424004240042
1600244004131006525240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000050204160355400388000080000800104004240042400424004240042
16002440041310010525240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000050205160356400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000050205160355400388000080000800104004240042400424004240042
16002440041311124225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000050205160345400388000080000800104004240042400424004240042