Firestorm: FCVTZU (scalar, integer, D to X) measurements

Code:

  fcvtzu x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	3	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	4	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	12	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	12	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20128	200	10000	20000	130068	130046	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	5	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130074	974	0	0	0	0	0	15	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10122	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	3	16	3	2	129525	10000	0	10000	10000	10100	130041	130057	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130024	119417	25	40100	10100	20000	10000	100	20118	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	0	2	16	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	1	0	130023	119417	46	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130103	0	130038	130039	125503	3	126271	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	1	0	3	0	1270	2	16	1	1	129591	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	15	130023	119417	25	40016	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20489	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	1	0	0	0	1289	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215123	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	130023	119417	25	40016	10010	20000	10000	10	20000	10000	50	6214979	14800719	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129579	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	15	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	3	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	2	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	17	2	1	129525	10000	10000	10000	10010	130047	130041	130039	130039	130039
30024	130038	974	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800140	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	15	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130039	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	6	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	973	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130044	130039	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, d8
  fcvtzu x1, d8
  fcvtzu x2, d8
  fcvtzu x3, d8
  fcvtzu x4, d8
  fcvtzu x5, d8
  fcvtzu x6, d8
  fcvtzu x7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40064	311	0	0	0	78	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	1	0	1	1	1	5117	2	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	87	264	32	25	240104	80100	160004	100	160020	500	1447562	1	40022	40041	40041	19977	6	19992	160962	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	6	1	1	1	5117	2	16	1	2	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	2	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	0	698	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40051	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	2	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	506	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	2	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	2	16	2	2	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	1	16	1	2	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	66	27	240116	80104	160012	100	160028	500	1440202	1	40032	40051	40052	19976	10	19989	160128	200	160038	200	160038	40051	40051	1	1	80201	100	99	100	80100	100	0	0	0	2	2	2	5128	3	24	3	3	40049	80004	80000	80100	40053	40052	40052	40052	40053
160204	40051	311	0	0	0	0	0	66	26	240116	80104	160012	100	160028	500	1440202	1	40032	40051	40051	19976	10	19989	160128	200	160038	200	160038	40051	40051	1	1	80201	100	99	100	80100	100	0	0	0	2	2	2	5128	2	24	3	2	40048	80004	80000	80100	40053	40053	40053	40053	40053
160204	40051	310	0	0	0	0	0	66	26	240326	80104	160012	100	160028	500	1440202	1	40032	40051	40051	19976	10	19989	160128	200	160038	200	160038	40051	40052	1	1	80201	100	99	100	80100	100	0	0	0	2	2	2	5127	2	24	2	3	40048	80004	80000	80100	40053	40053	40053	40052	40052

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	c2	cf	d2	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40055	310	0	0	0	0	0	42	0	0	42	48	240010	80010	160000	10	160200	50	1441840	0	0	40083	40041	40271	19996	3	20067	160010	20	160416	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	3	0	5020	4	24	16	0	0	25	26	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	322	0	0	0	0	0	3	0	0	158	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	25	16	0	0	25	25	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	249	0	0	945	25	240010	80390	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	25	16	0	0	25	25	40038	80000	80000	80010	40042	40042	40042	40200	40042
160024	40041	310	0	0	0	0	0	336	0	0	320	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	3	0	5020	0	28	16	0	0	14	26	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	18	352	0	805	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40119	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	3	0	5020	0	24	16	0	1	28	27	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	0	0	42	0	0	1468	25	240010	80010	160000	10	160000	50	1440000	1	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	15	52	0	0	27	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40123	310	0	0	0	2	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40353	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	25	16	0	0	14	30	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	12	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160804	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	25	16	0	0	14	27	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40358	310	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	15	16	0	0	27	14	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	6	0	0	0	0	33	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	1	0	3	0	5020	0	16	16	0	0	27	21	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTZU (scalar, integer, D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations