Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, D to X)

Test 1: uops

Code:

  fcvtzu x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007331622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000407321622538100010001000542542542542542
20045414124325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542
20045414124325300010002000200018000052254154124832742000200020005415411110011000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0304070b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020128200100002000013006813004611202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000500000013101021622129525100000100001000010100130039130039130039130039130039
302041300749740000015013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001012220000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101031632129525100000100001000010100130041130057130039130039130039
30204130038974000000013002411941725401001010020000100001002011810000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03181e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9accdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974101300231194174640010100102000010000102000010000506214979148000251130103013003813003912550331262713001020100002000020100002000013003813003811200211091010010100001010000103012702161112959110000100001000010010130039130039130039130039130039
300241300389740151300231194172540016100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002048913003813003811200211091010010100001010000100012891161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506215123148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540016100102000010000102000010000506214979148007191130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000012701161112957910000100001000010010130039130039130039130039130039
300241300389740151300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000003012701161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003821200211091010010100001010000000012701172112952510000100001000010010130047130041130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148001401130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000015012701161112952510000100001000010010130039130039130039130039130039
30024130038974001300231194172540010100102000010000102000010000506214979148000251130013013003813003912549831262683001020100002000020100002000013003813003811200211091010010100001010000600012701161112952510000100001000010010130039130039130039130039130039
30024130038973001300231194172540010100102000010000102000010000506214979148000251130013013004413003912549831262683001020100002000020100002000013003813003811200211091010010100001010000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, d8
  fcvtzu x1, d8
  fcvtzu x2, d8
  fcvtzu x3, d8
  fcvtzu x4, d8
  fcvtzu x5, d8
  fcvtzu x6, d8
  fcvtzu x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030f18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400643110007803225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100010111511721600400388000080000801004004240042400424004240042
16020440041310000872643225240104801001600041001600205001447562140022400414004119977619992160962200160032200160032400414004111802011009910080100100006111511721612400388000080000801004004240042400424004240042
16020440041310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711612400388000080000801004004240042400424004240042
160204400413110000069825240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414005111802011009910080100100000111511711612400388000080000801004004240042400424004240042
160204400413100000050625240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711612400388000080000801004004240042400424004240042
16020440041310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511721622400388000080000801004004240042400424004240042
16020440041310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511711612400388000080000801004004240042400424004240042
160204400413100000066272401168010416001210016002850014402021400324005140052199761019989160128200160038200160038400514005111802011009910080100100000222512832433400498000480000801004005340052400524005240053
160204400513110000066262401168010416001210016002850014402021400324005140051199761019989160128200160038200160038400514005111802011009910080100100000222512822432400488000480000801004005340053400534005340053
160204400513100000066262403268010416001210016002850014402021400324005140051199761019989160128200160038200160038400514005211802011009910080100100000222512722423400488000480000801004005340053400534005240052

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc2cfd2d5d6d9daddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553100000042004248240010800101600001016020050144184000400834004140271199963200671600102016041620160000400414004111800211091080010100030502042416002526400388000080000800104004240042400424004240042
160024400413220000030015825240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000502002516002525400388000080000800104004240042400424004240042
16002440041310000002490094525240010803901600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000502002516002525400388000080000800104004240042400424020040042
16002440041310000003360032025240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100030502002816001426400388000080000800104004240042400424004240042
160024400413100000018352080525240010800101600001016000050144000000400224011940041199963200211600102016000020160000400414004111800211091080010100030502002416012827400388000080000800104004240042400424004240042
16002440041311000004200146825240010800101600001016000050144000010400224004140041199963200211600102016000020160000400414004111800211091080010100000502001552002716400388000080000800104004240042400424004240042
16002440123310000200004225240010800101600001016000050144000011400224004140041199963200211600102016000020160000403534004111800211091080010100000502002516001430400388000080000800104004240042400424004240042
160024400413100000012004225240010800101600001016000050144000000400224004140041199963200211600102016000020160804400414004111800211091080010100000502002516001427400388000080000800104004240042400424004240042
16002440358310000000004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000502001516002714400388000080000800104004240042400424004240042
160024400413106000033004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010101030502001616002721400388000080000800104004240042400424004240042