Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, H to W)

Test 1: uops

Code:

  fcvtzu w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541494325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541408425300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541408325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc5branch mispredict (cb)cdcfd0icache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194142540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103421300131300411300381254763126246301002001000020366200100602000013003813003811202011009910010100100001000010000000000013101041632129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021612129525100000100001000010100130039130039130039130039130039
30204130041974000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000013101021622129525100000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000010000013101021622129525100000100001000010100130039130039130039130039130039
30204130038973000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013006113004311202011009910010100100001000010000000000013101022522129525100000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080e191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc2branch mispredict (cb)cfd5d6dbddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974020001300231194173840010100102000010000102000010000506214979148000250013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000201288117011129525100000100001000010010130057130043130039130039130040
30024130040974000601300231194172540010100102000010000102000010000506214979148000250013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000001270116011129525100000100001000010010130071130039130039130039130039
30024130038974000001300231194172540010100102000010000102000010000506214979148000250013001301300391300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000001270116011129525100000100001000010010130072130040130039130039130039
300241300381008000001300231194172540010100102000010000102023410049506215027148000250013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000001270116011129525100000100001000010010130093130039130042130039130040
30024130038973000001300231194172540010100102000010000102000010000506214979148000250013001501301191301101255979126398301782010000200002010000202451302791301393120021109101001010000101000003001270116011129525100000100001000010010130091130039130039130039130039
30024130039974000901301031194172540010100102000010000102000010000506214979148000250013001601301221300461255043126271303412010000200002010000200001300411300401120021109101001010000101000000001270116011129525100000100001000010010130055130041130039130039130039
30024130038974000011213273012044664540204100462010010050102000010000506214979148000250013001301301861300421254983126268300102010000200002010000200001300381300381120021109101001010000101000000001270116011129525100000100001000010010130061130039130039130039130039
30024130038974000001300231194172540010100102000010000102000010000506214979148000250013001301300381300381254983126268300102010000200002010000200001300391300381120021109101001010000101000000001270116011129525100000100001000010010130136130078130042130039130039
300241300381008002001300231194172540010100102000010000102000010000506214979148000250113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000003001270116011129525100000100001000010010130039130039130039130039130039
3002413012110081002101300231194172540010100102000010000102000010000506214979148003610113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000001270116011129525100020100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, h8
  fcvtzu w1, h8
  fcvtzu w2, h8
  fcvtzu w3, h8
  fcvtzu w4, h8
  fcvtzu w5, h8
  fcvtzu w6, h8
  fcvtzu w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)03191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9facc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044004129900322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004130000532524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004130000532524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511711600400388000080000801004004240042400424004240042
1602044004129900322524010480100160004100160020500144013204008640041400411997706199921601202001600322001600324004140041118020110099100801001003111511701600400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004129900322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042
1602044004129900322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc2cfd0d2icache miss (d3)d5d6d9dadbddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244004331000042252400108001016000010160000501440000004002240122400411999632002116001020160000201600004004140041118002110910800101000005020000616000534003880000080000800104012240042400424004240042
16002440041310000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010002105020000316000534003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101010005020000516000554003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000305020000516000534003880000080000800104004240042400424004240042
160024400413210001111252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000005020000316000534003880000080000800104004240042400424004240042
160024400413100041742252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000905020000316000354003880000080000800104004240042400424004240042
1600244004131100042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000045020300516000634003880000080000800104004240042400424004240042
160024400413100148702524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000050200105162103540038800002080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000005020000416000454003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000005020000316000354003880000080000800104004240042400424004240042