Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, H to X)

Test 1: uops

Code:

  fcvtzu x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541512432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454140432530001000200020001800052654154124832742000200020005415411110011000007311611538100010001000542542542542542
200454150432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454150432530001000200020001800052254154124832742000200020005415411110011000037311611538100010001000542542542542542
200454140432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542
200454150432530001000200020001800052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03040b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547691262893010020010000200002021000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000013006911941725401001010020000100001002000010000500621497914801034013001313003813004512547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130042130039
30204130038974000000013002311941725401201010020000100001002000010000500621497914801034113001313008813004012547631262463010020010000200002001000020000130038130038112020110099100101001000010000100020000131012162212952710000100001000010100130039130039130039130039130040
30204130038974100000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000201292001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547691267493010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162312952510000100001000010100130039130039130039130039130039
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812550131262463010020010000200002001000020000130038130038112020110099100101001000010000100000000133612162212952510000100001000010100130039130072130039130042130039
30204130038974000000013002311941725401001010020000100001002000010000500621544514806243013004213003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012163212952510000100001000010100130039130039130039130039130039
30204130038974000000013002311946125401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000300131012162212952510000100001000010100130039130039130039130039130039
30204130038974000000013005211941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000133712162212952510000100001000010100130039130039130039130039130039
302041300389740000810013002311941725401001010020000100001002000010049500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a7a8a9acc5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126319300102010000200002010000200001300381300381120021109101001010000100100000000012703162312952510000100001000010010130039130039130039130043130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012703164312952810000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126281301022010000200002010066200001300381300381120021109101001010000100100000000012703163412952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012702163412952510000100001000010010130039130039130039130039130039
300241300381111000000130023119417254001010013200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012703162312952510000100001000010010130039130039130039130039130039
30024130040974000000130023119417254001010010200001000110200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012704163312952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001601300381300381254983126323300102010000200002010000200001300381300381120021109101001010000100100000000012703163212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126306300102010000200002010000200001300381300381120021109101001010000100100000000012702162312962210000100001000010010130039130039130039130039130040
30024130040974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126323300102010000200002010000200001300381300381120021109101001010000100100000000012703163212952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126318300102010000200002010000200001300381300381120021109101001010000100100000000012702163212952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, h8
  fcvtzu x1, h8
  fcvtzu x2, h8
  fcvtzu x3, h8
  fcvtzu x4, h8
  fcvtzu x5, h8
  fcvtzu x6, h8
  fcvtzu x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6inst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400412990000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400413000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400413000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400412990000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400413000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400412990000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400412990000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400412990000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041310000012012725240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
160204400413000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f6061696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8acc2cfd0d2icache miss (d3)d5d6d9daddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005530000005182524001080010160000101600005014400000004002204177341715204991572101116454620162434201645364187941312221800211091080010100201382505362009110188011314412668233180000800104140041808420204188141941
160024420313252423259220243356435246943823791638681016411450147428200040022040041400411999632002116001020160000201653164163742105261800211091080010100000050200005161065401218000080000800104004240042400424004240042
16002440041310000042252400108001016000010160000501440000000400220400414004119996320021160010201600002016000040041400411180021109108001010000162050200006160054400388000080000800104004240042400424004240042
160024400413000000422524001080010160192101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000050200005160054400388000080000800104004240042400424004240042
160024400413000000422524001080010160000101600005014400000104015204004140133199963200211600102016000020160000400414004111800211091080010100010050200005160054400388000080000800104004240042400424004240042
160024400413000000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000050200006160055400388000080000800104004240042400424004240042
160024400412990000842524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010102020050560005160054400388000080000800104004240042400424004240042
1600244004130000120842524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100003050200004160056400388000080000800104004240042400424004240042
1600244004129900120842524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000050200005160045400388000080000800104004240042400424004240042
1600244004130000240422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000050200006160155400388000080000800104004240042400424004240042