Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, S to W)

Test 1: uops

Code:

  fcvtzu w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8a9accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414064253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000107311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2c5branch mispredict (cb)cdcfd0d5d6daddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254836126242301002001000220006200100022000613003913003811202011009910010100100001000010000000001111317021601112953410000100001000010100130039130039130039130039130043
3020413003897600000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812548371262423010020010002200062001000020000130043130038112020110099100101001000010000100000003000001310121602212957710000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310121602212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013004113003811202011009910010100100001000010000000000011310121602212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126332301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310121602212952510000100001000010100130039130039130039130039130039
302041300389740000001300311194172540128101002000010000100200001000050062149791480103401300131300381300381254763126260301002001000020000200100002000013003813003811202011009910010100100001000010000000001001310121602212952510000100001000010100130039130039130039130039130040
302041300399740000001300231194172540100101002000010000100200001000050062149791480103411300141300381300381254763126294301002001000020000200100002000013003913003811202011009910010100100001000010004012440100001310121602212952510000100001000010100130040130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126295301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310121602212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254793126284301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310121602212953210000100001000010100130039130042130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126276301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310121602212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000130023119417254001010010200001000010200001000050622454814802413113001301300381300381255593126268300102010000200002010000200001300381300381120021109101001010000100010000300012972161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301301281300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130042130045130040130039
30024130038974000000130023119417254001010010200001000010200001000050621507514800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038975000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268301722010000200002010000200001300381300381120021109101001010000100010000003012701161112952510003100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621507514800025113001301300381300381254983126293300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130090
30024130038974000000130023119417254001010010200001000010200001000050622388714803081113001301300381300381255533126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038975000000130023119417254001010010200001000010200001004950621584314800138013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621502714800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621502714800025113001301300381300381254983126270300102010000200002010000200001300381300381120021109101001010000100010000000012701162112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, s8
  fcvtzu w1, s8
  fcvtzu w2, s8
  fcvtzu w3, s8
  fcvtzu w4, s8
  fcvtzu w5, s8
  fcvtzu w6, s8
  fcvtzu w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006231000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440102310000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151174701600400388000080000801004004240042400424004240042
1602044004131100000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131010000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131100000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131100000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131100000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03040708191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8a9accfd5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440055311000012422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020141671240038800000080000800104004240042400424004240042
1600244004131000000422524001080010160000101600005014400000140022400414004119996320021160010201600002016000040041400411180021109108001010000005020716121140038800000080000800104004240042400424004240042
160024400413100000042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000000502051691040038800000080000800104004240042400424004240042
1600244004131000010422524001080010160000101600005014400000140022400414004119996320021160010201600002016000040041400411180021109108001010000005020121611840038800000080000800104004240042400424004240042
16002440041310000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100000050201116111140038800000080000800104004240042400424004240042
16002440041310000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100000050201016111040038800000080000800104004240042400424004240042
1600244004132200000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000005020111611740038800000080000800104004240042400424004240042
1600244004131100000422524001080010160000101600005014400000140022400414004119996320021160010201600002016000040041400411180021109108001010000005020716111240038800000080000800104004240042400424012840042
1600244004131100000422524001080010160000101600005014400000140022400414004119996320021160010201600002016000040041400411180021109108001010000005022916111140038800000080000800104004240042400424004240042
16002440041310000004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000050201116111240038800000080000800104004240042400424012640042