Firestorm: FCVTZU (scalar, integer, S to X) measurements

Code:

  fcvtzu x0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	0	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	2	0	0	0	410	0	73	2	16	2	2	538	1099	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	0	0	0	138	25	3000	1096	2000	2000	18000	1	522	541	541	273	7	320	2208	2000	2000	541	541	1	1	1001	1000	0	2	0	0	2	368	0	88	2	16	2	2	538	1000	1000	1000	542	542	617	617	542
2004	541	5	0	0	0	0	0	0	18	0	186	25	3000	1000	2000	2000	18000	1	522	541	620	248	3	274	2208	2000	2000	541	541	1	1	1001	1000	2	0	0	1	0	3	0	73	2	16	2	2	538	1000	1000	1000	542	542	542	542	649
2004	623	5	0	0	0	0	0	0	0	0	65	25	3000	1000	2000	2000	18000	1	588	541	541	248	11	274	2000	2000	2000	541	623	2	1	1001	1000	0	0	0	1	0	220	0	73	2	16	2	2	538	1000	1000	1000	542	625	618	620	623
2004	623	5	0	0	0	0	0	0	88	0	192	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	0	0	73	2	16	2	3	538	1000	1000	1000	542	542	621	542	542
2004	541	4	0	1	0	0	0	3	88	1	64	25	3286	1000	2000	2000	18000	1	578	541	541	272	3	320	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	1	0	0	0	73	2	16	3	2	538	1000	1000	1000	542	624	542	623	624

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	2	130023	119420	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130071	130040	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	4	17	6	9	129531	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130056	130043	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	6	16	5	6	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	3	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130083	130050	1	1	20201	100	99	100	10100	10000	100	0	10000	0	51	0	0	0	0	1314	4	16	5	6	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	973	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130085	130056	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	9	16	7	9	129530	10000	10000	10000	10100	130039	130039	130039	130039	130083
30204	130038	974	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130042	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	8	16	8	8	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130093	130044	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	8	16	7	8	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	2	130023	119415	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130014	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130099	130051	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	8	16	8	8	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130080	130044	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	8	16	7	9	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	130038	130038	125507	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	8	16	7	8	129601	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	2	130023	119417	25	40100	10100	20000	10000	116	20000	10000	500	6217043	14802524	130013	130038	130082	125480	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1314	8	16	7	4	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	973	0	0	0	0	0	0	130026	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	1	1270	2	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119424	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130041	130039	130039	130039	130039
30024	130038	974	0	0	0	6	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	12	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130069	130043	130039
30024	130038	974	0	0	0	0	0	0	130023	119424	25	40010	10010	20000	10000	10	20000	10000	50	6215445	14800025	0	130013	0	130039	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130039	2	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130040	130039	130039
30025	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125512	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	2	16	2	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130025	119417	25	40010	10010	20000	10000	10	20000	10000	55	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130024	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130017	0	130039	130039	125498	3	126277	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	973	0	0	0	0	0	0	130027	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	6	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130069	130047	130039
30024	130038	974	0	0	0	0	0	0	130027	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130045

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, s8
  fcvtzu x1, s8
  fcvtzu x2, s8
  fcvtzu x3, s8
  fcvtzu x4, s8
  fcvtzu x5, s8
  fcvtzu x6, s8
  fcvtzu x7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40066	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	1	16	1	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	2	1	40103	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	5	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	1	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	1	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40054	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	2	2	0	0	0	5020	0	3	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	5	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	2	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	2	2	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	2	0	5020	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTZU (scalar, integer, S to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations