Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, S to X)

Test 1: uops

Code:

  fcvtzu x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)0307080a0b191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a1a7a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541400000000432530001000200020001800015225415412483274200020002000541541111001100000000007321622538100010001000542542542542542
2004541400000000432530001000200020001800015225415412483274200020002000541541111001100000000007321622538100010001000542542542542542
2004541400000000432530001000200020001800015225415412483274200020002000541541111001100000000007321622538100010001000542542542542542
2004541400000000432530001000200020001800015225415412483274200020002000541541111001100000000007321622538100010001000542542542542542
200454140000000043253000100020002000180001522541541248327420002000200054154111100110000200041007321622538109910001000542542542542542
2004541400000000138253000109620002000180001522541541273732022082000200054154111100110000200236808821622538100010001000542542617617542
200454150000001801862530001000200020001800015225416202483274220820002000541541111001100020010307321622538100010001000542542542542649
2004623500000000652530001000200020001800015885415412481127420002000200054162321100110000001022007321622538100010001000542625618620623
200462350000008801922530001000200020001800015225415412483274200020002000541541111001100000000007321623538100010001000542542621542542
20045414010003881642532861000200020001800015785415412723320200020002000541541111001100000010007321632538100010001000542624542623624

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0304080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000000021300231194202540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130071130040112020110099100101001000010001000000000013144176912953110000100001000010100130039130039130039130039130039
30204130038974000000021300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130056130043112020110099100101001000010001000000000013146165612952510000100001000010100130039130039130039130039130039
302041300389740000030213002311941725401001010020000100001002000010000500621497914801034130013130038130038125476312624630100200100002000020010000200001300831300501120201100991001010010000100010000051000013144165612952510000100001000010100130039130039130039130039130039
30204130038973000000021300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130085130056112020110099100101001000010001000000000013149167912953010000100001000010100130039130039130039130039130083
30204130038974000000021300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130042130038112020110099100101001000010001000000000013148168812952510000100001000010100130039130039130039130039130039
30204130038974000000021300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130093130044112020110099100101001000010001000000000013148167812952510000100001000010100130039130039130039130039130039
30204130038974000000021300231194152540100101002000010000100200001000050062149791480103413001413003813003812547631262463010020010000200002001000020000130099130051112020110099100101001000010001000000000013148168812952510000100001000010100130039130039130039130039130039
30204130038974000000021300231194172540100101002000010000100200001000050062149791480103413001313003813003812547631262463010020010000200002001000020000130080130044112020110099100101001000010001000000000013148167912952510000100001000010100130039130039130039130039130039
30204130038974000000021300231194172540100101002000010000100200001000050062149791480103413001313003813003812550731262463010020010000200002001000020000130038130038112020110099100101001000010001000000000013148167812960110000100001000010100130039130039130039130039130039
30204130038974000000021300231194172540100101002000010000116200001000050062170431480252413001313003813008212548031262463010020010000200002001000020000130038130038112020110099100101001000010001000000000013148167412952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a7a8a9acc2branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389730000001300261194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000000112702161112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194242540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000000012701161112952510000100001000010010130041130039130039130039130039
3002413003897400060013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000120000012701161112952510000100001000010010130039130039130069130043130039
300241300389740000001300231194242540010100102000010000102000010000506215445148000250130013013003913003812549831262683001020100002000020100002000013003813003921200211091010010100001010000000000012701161112952510000100001000010010130039130039130040130039130039
300251300389740000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812551231262683001020100002000020100002000013003813003811200211091010010100001010000000000012702162112952510000100001000010010130039130039130039130039130039
300241300389740000001300251194172540010100102000010000102000010000556214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000001300241194172540010100102000010000102000010000506214979148000250130017013003913003912549831262773001020100002000020100002000013003813003811200211091010010100001010000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389730000001300271194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740006001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000000012701161112952510000100001000010010130039130039130069130047130039
300241300389740000001300271194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000000000012701161112952510000100001000010010130039130039130039130039130045

Test 3: throughput

Count: 8

Code:

  fcvtzu x0, s8
  fcvtzu x1, s8
  fcvtzu x2, s8
  fcvtzu x3, s8
  fcvtzu x4, s8
  fcvtzu x5, s8
  fcvtzu x6, s8
  fcvtzu x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030818191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a8acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006630000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117116104003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016004003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016214010380000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013214002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016004003880000080000801004004240042400424004240042
1602044004129900000322524010480100160004100160020500144013214002204004140041199775619992160120200160032200160032400414004111802011009910080100100000001115117016104003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016004003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016004003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013214002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016104003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016004003880000080000801004004240042400424004240042
1602044004130000000322524010480100160004100160020500144013204002204004140041199770619992160120200160032200160032400414004111802011009910080100100000001115117016004003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a9accfd0d5d6daddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005430004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010102200050200316011400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000050205116011400388000080000800104004240042400424004240042
1600244004129904225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004121800211091080010100000050200116221400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000050200116011400388000080000800104004240042400424004240042
1600244004129904225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000050200116011400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100000050200116011400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100000050200116011400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000050200116011400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000050200116011400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100002050200116011400388000080000800104004240042400424004240042