Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (vector, integer, 2S)

Test 1: uops

Code:

  fcvtzu v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230103254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303724061254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037230103254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303724079254725100010001000398160030180303730372414328951000100010003037303711100110000373216222629100030383038303830383038
1004303723061254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372312105254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037231261254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723061254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723061254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303724061254725100010001000398160030180303730372414328951000100010003037303711100110000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzu v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233008929547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
10204300372331206129547251010010010000100100005004277160130018300373003728271728741101002001000820010008300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
10204300372330025129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003007130038300383003830038
1020430037232008929547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
10204300372321206129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710021611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038
1020430037233006129547251010010010005100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037233000000462829493134100711210056141105093428632213023430368304162830725288791091224111502210652304183041781100211091010100001022211950385103974629919210000103051230512304663050930513
100243022323611061452880061295472510010101000010100006042771601300903050830554283265028804100102010000201000030037300371110021109101010000100000064003162229629010000103003830038300383003830038
100243003723300018008229547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000064002162229629010000103003830038300383003830038
10024300372410000006129547251001010100001010000504277160130018300713003728286328767100102010000201000030037300371110021109101010000100000064042162229629010000103003830038300383003830038
100243003724100045006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000064002162229629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000364002162229629010000103003830038300383003830038
100243003723200000023029547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000064002162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000064002162229629010000103003830038300383003830038
10024300372250000004962954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000012664002162229629010000103003830038300383003830038
10024300372240000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000064002162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzu v0.2s, v8.2s
  fcvtzu v1.2s, v8.2s
  fcvtzu v2.2s, v8.2s
  fcvtzu v3.2s, v8.2s
  fcvtzu v4.2s, v8.2s
  fcvtzu v5.2s, v8.2s
  fcvtzu v6.2s, v8.2s
  fcvtzu v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039155004203025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
8020420039156006303025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
8020420039155003903025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
802042003915510607925801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
802042003916100007925802121008000810080020500640132120020200392003999776999080120200803482008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
80204200391550024050525801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
8020420039155000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036211800001002004020040200402004020040
802042003915500003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
80204200391550027017125801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040
8020420039156003603025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118016002003600800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e1f3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511550000120367002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502007165320036080000102004020040200402004020040
800242003915500000040002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502004163520036080000102004020040200402004020040
800242003915500000040002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502004165520036080000102004020040200402004020040
800242003915600000082002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502005165520036080000102004020040200402004020040
800242003915500000040002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502005164620036080000102004020040200402004020040
800242003915500000054002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502006165520036080000102004020040200402004020040
800242003924800000040002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502003164620036080000102004020040200402004020040
800242003915500000061002580010108000010800005064000001020020200392003999963100198001020800002080000200392003911800211091010800001000000000502005165520036080000102004020040200402004020040
800242003915500000040002580010108000010800005064000011020020200392003999963100198001020800002080000200392003911800211091010800001000000000502005166420036080000102004020040200402004020040
800242003915500000082002580010108000010800005064000000020020200392003999963100198001020800002080000200392003911800211091010800001000000000502003165520036080000102004020040200402004020040