Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (vector, integer, 8H)

Test 1: uops

Code:

  fcvtzu v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724006125472510001000100039816003018303730372414328951000100010003037303711100110001073216222629100030383038303830383038
1004303724006125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303724006125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037240126125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723006125472510001000100039816003018303730372414328951000100010003037303711100110000373216222629100030383038303830383038
10043037240666125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004308523006125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037230126125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303723006125472510001000100039816003018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303724006125472510001000100039816003018303730372414328951000100010003037303711100110001073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzu v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100137101161129633000100001003003830038300383003830038
1020430037233012629547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
1020430037232034029547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
1020430037233074529547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
1020430037233083929547251010010010000100100005004277160130018300373003728264328745101002001000020010182300373003711102011009910010010000100037101161129633000100001003003830038300383003830038
10204300372330161629547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
1020430037233036729547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
1020430037233043629547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
1020430037233016829547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038
102043003723312102829547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633000100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225067295472510010101000010100005042771603001803003730037282860328767100102010000201000030037300371110021109101010000100006401116332962910000103003830038300383003830038
1002430037225096529547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010200640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722506729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316332962910000103003830038300383003830038
100243003722406729547251001010100001010000504277160300180300373003728286032876710010201000020100003003730037111002110910101000010000640316442962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzu v0.8h, v8.8h
  fcvtzu v1.8h, v8.8h
  fcvtzu v2.8h, v8.8h
  fcvtzu v3.8h, v8.8h
  fcvtzu v4.8h, v8.8h
  fcvtzu v5.8h, v8.8h
  fcvtzu v6.8h, v8.8h
  fcvtzu v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006815500000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151182163320036800001002004020040200402004020040
802042003915500000582580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183163420036800001002004020040200402004020040
8020420039155000001182580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183163320036800001002004020040200402004020040
802042003915500000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183164320036800001002004020040200402004020040
802042003915500000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000211151183164520036800001002004020040200402004020040
8020420039155000001392580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183163420036800001002004020040200402004020040
802042003915500000722580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183164420036800001002004020040200402004020040
8020420039155000001562580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151183164420036800001002004020040200402004020040
802042003916100000302580108100800081008002050064013212002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151184162420036800001002004020040200402004020040
802042003915600012024225801081008000810080020500640132120020200392003999771299908012020080032200800322003920039118020110099100100800001000000011151184165420036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391550402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000050201616011122003680000102004020040200402004020040
8002420039156124452580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010010050201416013112003680000102004020040200402004020040
80024200391550402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000050201316012112003680000102004020040200402004020040
80024200391560402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000050201416013122003680000102004020040200402004020040
8002420039155040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000005020101606112003680000102004020040200402004020040
80024200391550402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010010050201116013112003680000102004020040200402004020040
8002420039155068258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000005020131607122003680000102004020040200402004020040
80024200391550402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000050201116013112003680000102004020040200402004020040
800242003915501242580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000050201216012112003680000102004020040200402004020040
80024200391560166258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000005020121601292003680000102004020040200402004020040