Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVT (H to D)

Test 1: uops

Code:

  fcvt d0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372212612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
1004303723135612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
100430372260612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
1004303723751452547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037220822547251000100010003981600301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037220612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
10043037220612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038
1004303722126612547251000100010003981601301830373037241432895100010001000303730371110011000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvt d0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000300071011611296330100001003003830038300383003830038
10204300372250000165295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037224000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037260000000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103007230038300383003830038
1002430037260000000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037260000000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402172229629010000103003830038300383003830038
10024300372410000000001242954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
10024300372410000000004082954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037241000000000842954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402242229629010000103003830038300383003830038
1002430037241000000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037233000000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229701010000103003830038300383003830038
10024300372320000000002542954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037229000000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvt d0, h8
  fcvt d1, h8
  fcvt d2, h8
  fcvt d3, h8
  fcvt d4, h8
  fcvt d5, h8
  fcvt d6, h8
  fcvt d7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150110000158258010810080008100800205006401320200202003920039997714999080120200800322008003220039200391180201100991001008000010000003111511811611200360800001002004020040200402004020040
80204200391501100103042803121008000810080128500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000111511811621200360800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000003111511811611200360800001002004020040200402004020040
802042003914911000062225801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000111511841611200361800001002004020040200402004020040
802042003915011000049725801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000100111511811611200360800001002004020040200402004020040
802042003915011000127225801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000040111511812611200750800001002004020040200402004020091
80204200391501100003044801081008000810080020500641008020020200992003999776999080120200800322008003220039200391180201100991001008000010000000111511811612200360800001002004020040200402004020040
802042003915011000013925801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010002000111511811611200360800001002004020040200402004020040
80204200391501100005325801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000111511811611200360800001002004020040200402004020040
802042003915011000013925801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000111511811612200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115020000211258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000050201016810222003680000102004020040200402004020040
800242003915000000402580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100000502091669182003680000102004020040200402004020040
80024200391500000040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000050202116621212003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020211679212003680000102004020040200402004020040
8002420039150001210804025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020916821212003680000102004020040200402004020040
80024200391500000040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000050202116721212003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001007015020211682192003680000102004020040200402004020040
8002420039150000004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020916721212003680000102004020040200402004020040
80024200391500000051525800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020221679212003680000102004020040200402004020040
80024200391500000012625800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000005020916822222003680000102004020040200402004020040