Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVT (H to S)

Test 1: uops

Code:

  fcvt s0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e5051schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037231261254730212510001000100039816013018303730372414328951000100010003037303711100110000073316112629100030383038303830383038
10043037223361254702510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037233361254702510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722061254702510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722061254702510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722061254702510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723061254702510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722061254702510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230612547025100010001000398160130183037303724143289510001000100030373037111001100018073116112629100030383038303830383038
1004303723061254702510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvt s0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030f1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010080071011611296330100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100100071011611296330100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001002624071011611296330100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010093071011611296330100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100715071011611296330100001003003830038300383003830038
102043003722500612954725101001001000010010000500427716003001830037300372828632874510100200100002001000030037300371110201100991001001000010060071011611296330100001003003830038300383003830038
1020430037233002392954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010070071011611296330100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100313071011611296330100001003003830038300383003830038
1020430037224006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100313071011611296330100001003003830038300383003830038
1020430037225006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100253071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500018929547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
100243003722500061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010003806402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvt s0, h8
  fcvt s1, h8
  fcvt s2, h8
  fcvt s3, h8
  fcvt s4, h8
  fcvt s5, h8
  fcvt s6, h8
  fcvt s7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006115002202580108100800081008002050064013220020200902003999776999080120200800322008003220039200391180201100991001008000010003800111511811620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000100111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000026111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
80204200391500302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010001075111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040
8020420039150030258010810080008100800205006401322002020039200399977699908012020080032200800322003920039118020110099100100800001000000111511801620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020191618232003680000102004020040200402004020040
80024200391501240258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020181623132003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020231618232003680000102004020040200402004020040
80024200391500230258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010035020181622182003680000102004020040200902004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020171623182003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020231618232003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020231623232003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020221624242003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002009020039118002110910108000010105020131623182003680000102004020040200402004020040
8002420039150040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020141623182003680000102004020040200402004020040