Firestorm: FDIV (scalar, H) measurements

Code:

  fdiv h0, h0, h1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	7037	52	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	2	16	4	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	52	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	60	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	24	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	12	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	3	16	3	3	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	0	61	5757	25	1000	1000	1000	245957	1	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	2	16	3	3	6726	1000	7038	7038	7038	7038	7038

Test 2: Latency 1->2

Code:

  fdiv h0, h0, h1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70037	524	0	0	0	0	0	0	504	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	0	0	402	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70085	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	6	2	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70181	70038	70086
10204	70225	543	0	0	0	0	0	0	600	0	61	59757	25	10100	100	10012	122	10117	500	2504957	0	70018	70319	70273	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	4	0	932	6	137	2	2	70312	25	10000	100	70747	70794	70798	70748	70748
10204	70750	548	1	1	2	1	16	15	2478	1320	82	59757	25	10191	100	10000	100	10312	500	2504957	0	70198	70037	70132	68393	3	69253	10100	200	10673	200	20000	70037	70792	2	1	10201	100	99	100	100	10000	100	0	8	0	1	1	4	8940	2	0	819	5	16	1	2	69725	25	10000	100	70038	70798	70038	70038	70038
10204	70037	543	0	0	0	0	3	10	2199	504	3233	59597	320	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	0	0	0	291	0	61	59757	44	10100	100	10000	100	10000	605	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20114	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	0	0	0	0	710	1	16	2	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	0	0	0	501	0	61	59747	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20218	70085	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	0	0	393	88	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20112	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	0	0	513	88	82	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68532	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70086	70038
10204	70037	525	0	0	0	0	1	0	465	0	293	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	0	710	1	16	1	2	69725	0	10000	100	70038	70038	70038	70038	70038

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70037	524	0	0	747	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	86	0	0	640	2	16	2	2	69792	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	80	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	71	3	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68434	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	37	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	0	9	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	85	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	0	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	77	0	1	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	313	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	84	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	536	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	76	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	80	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	0	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	86	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038

Test 3: Latency 1->3

Code:

  fdiv h0, h1, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70037	525	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	82	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	83	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	126	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70084	1	1	10201	100	99	100	100	10000	100	80	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	675	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70070	70037	1	1	10201	100	99	100	100	10000	100	83	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	61	59757	25	10100	100	10016	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10058	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	81	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	78	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	24	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	79	0	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	9	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	9	0	0	710	1	16	1	1	69725	0	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	69725	0	10000	100	70071	70038	70038	70038	70038

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70037	524	0	0	0	2	718	59757	25	10010	10	10000	10	10000	50	2504957	1	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	10	16	12	7	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	108	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70180	70037	68415	3	68767	10010	20	10000	20	20000	70084	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	5	16	10	10	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	588	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	12	16	10	10	69726	10000	10	70038	70038	70085	70038	70038
10024	70037	525	0	9	0	2	548	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	11	16	10	11	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	411	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	11	16	10	10	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	567	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70037	70037	68451	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	10	16	10	10	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	2307	59757	25	10010	10	10000	10	10039	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	10	16	5	10	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	616	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	643	5	16	12	5	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	1966	59757	25	10010	10	10000	11	10000	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	12	16	12	7	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	0	0	2	261	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	0	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	643	10	16	10	10	69726	10000	10	70038	70038	70038	70038	70038

Test 4: throughput

Count: 8

Code:

  fdiv h0, h8, h9
  fdiv h1, h8, h9
  fdiv h2, h8, h9
  fdiv h3, h8, h9
  fdiv h4, h8, h9
  fdiv h5, h8, h9
  fdiv h6, h8, h9
  fdiv h7, h8, h9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80043	601	0	0	0	0	0	0	0	0	0	54	96	80100	100	80000	100	80000	500	640000	80024	80204	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	6	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	600	1	0	0	0	0	0	12	0	0	434	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	599	0	0	0	0	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	4	2	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	599	0	0	0	0	0	0	0	0	0	877	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	2	80035	0	80000	100	80044	80044	80044	80259	80044
80204	80043	600	0	0	0	0	0	0	51	352	0	54	25	80100	100	80112	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	0	0	0	0	54	25	80209	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80078	0	80000	100	80256	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80192	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	2	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5162	1	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	599	0	0	0	0	0	0	0	0	0	54	97	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	2	0	0	0	0	5110	1	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	1	0	0	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	5	1	80201	100	99	100	100	80000	100	0	0	0	3	0	5110	1	16	1	1	80035	0	80000	100	80044	80044	80044	80044	80044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80043	600	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80022	10	9	10	10	80000	10	0	0	5020	2	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	600	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	0	0	0	0	529	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	600	0	0	0	0	0	54	25	80010	10	80000	11	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	3	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	1	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	2	2	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	0	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	2	16	2	2	80036	0	80000	10	80044	80044	80044	80044	80044
80024	80043	600	0	0	0	0	0	54	25	80010	10	80000	10	80000	50	640000	0	80024	80043	80043	69986	0	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	5020	1	16	1	1	80036	0	80000	10	80044	80044	80044	80044	80044

FDIV (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations