Firestorm: FDIV (scalar, S) measurements

Code:

  fdiv s0, s0, s1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	54	73	2	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	201	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	3	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	32	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	21	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	61	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	0	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	1	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038

Test 2: Latency 1->2

Code:

  fdiv s0, s0, s1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	599	0	0	0	61	69721	455	10203	141	10006	100	10152	500	2864300	1	80018	80037	80037	78344	0	3	78772	10148	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	213	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	231	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	726	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	123	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	108	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	102	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10152	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	108	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	511	2864300	0	80065	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	180	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	99	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69703	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20140	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	105	0	710	1	16	1	1	79677	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	726	69721	25	10010	10	10000	11	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10038	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	726	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	690	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80070
10024	80037	600	0	726	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	80070	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10022	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	6	61	69721	25	10010	10	10000	11	10000	50	2864300	0	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	0	10	10	10000	10	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038

Test 3: Latency 1->3

Code:

  fdiv s0, s1, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	80037	80037	78344	3	78745	10160	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80083
10204	80037	600	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	61	69721	25	10100	104	10015	100	10000	500	2864300	0	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	61	69721	25	10100	100	10000	100	10000	562	2864300	0	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80072	80038	80038	80038
10204	80037	600	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	599	0	705	0	768	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	8	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	321	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	468	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10022	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	351	0	726	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	46	3	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80072	599	0	288	0	726	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	570	0	764	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78415	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	870	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	330	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	516	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	393	0	61	69721	25	10010	10	10000	10	10000	50	2864300	0	80018	3	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	79677	10000	10	80038	80038	80038	80038	80038

Test 4: throughput

Count: 8

Code:

  fdiv s0, s8, s9
  fdiv s1, s8, s9
  fdiv s2, s8, s9
  fdiv s3, s8, s9
  fdiv s4, s8, s9
  fdiv s5, s8, s9
  fdiv s6, s8, s9
  fdiv s7, s8, s9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80046	599	0	0	0	138	0	720	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	2	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	0	462	0	1252	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	0	327	0	748	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	1	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	0	474	0	720	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	0	300	0	245	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	0	237	0	720	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	0	576	0	55	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	0	1	80036	0	80000	100	80045	80045	80099	80045	80045
80204	80044	599	0	0	0	762	0	55	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	0	0	0	55	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	0	0	0	76	0	25	80100	100	80000	100	80000	500	640000	80025	80044	80044	69964	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	5	0	6	0	0	5110	1	16	1	1	80036	0	80000	100	80045	80045	80045	80045	80045

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80044	599	9	55	25	80010	10	80000	10	80000	50	640000	1	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	2	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	9	16	8	5	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	6	16	5	6	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	720	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80169	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	5	16	7	7	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	530	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	8	16	7	7	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	6	16	8	6	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	1	8	16	6	5	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5041	0	5	16	8	8	80035	80000	10	80045	80045	80045	80099	80045
80024	80044	600	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80166	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	3	0	5020	0	7	16	6	5	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70068	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	7	16	6	5	80035	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	55	25	80010	10	80000	10	80000	50	640000	0	80025	80044	80044	69986	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	8	16	8	8	80035	80000	10	80045	80045	80045	80045	80045

FDIV (scalar, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations