Firestorm: FDIV (vector, 2S) measurements

Code:

  fdiv v0.2s, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	8037	60	0	82	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	290	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8084	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8086	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	2	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1112	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7921	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038
1004	8037	60	0	61	6721	25	1000	1000	1000	281300	1	8018	8037	8037	7494	3	7895	1000	1000	2000	8037	8037	1	1	1001	1000	0	0	73	1	16	1	1	7677	1000	8038	8038	8038	8038	8038

Test 2: Latency 1->2

Code:

  fdiv v0.2s, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	599	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	0	80037	80037	78351	7	78740	10100	200	10008	200	20016	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	79888	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	0	80037	80037	78351	6	78741	10100	200	10008	200	20016	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	79688	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	0	80037	80037	78351	7	78741	10100	200	10008	200	20016	80037	80037	1	1	10201	100	99	100	100	10000	100	1	0	0	1	1	1	718	0	16	0	0	79687	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	0	80037	80037	78351	6	78741	10100	200	10008	200	20016	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	79688	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	0	80037	80037	78351	7	78740	10100	200	10008	200	20016	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	6	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	0	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	0	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	14	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	0	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	61	69721	25	10100	100	10000	124	10000	500	2864300	1	80018	0	80037	80037	78344	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	1	80018	0	80037	80037	78344	3	78780	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	599	0	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80069
10024	80037	599	0	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	0	61	69721	25	10012	10	10000	10	10000	50	2864300	1	80018	3	80037	80037	78366	3	78767	10010	20	10215	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	10123	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10025	80037	599	0	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	600	9	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	264	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	564	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	23	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	381	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038
10024	80037	599	96	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	0	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	3	640	2	16	2	2	79677	0	10000	10	80038	80038	80038	80038	80038

Test 3: Latency 1->3

Code:

  fdiv v0.2s, v1.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	80037	600	0	0	0	0	0	0	120	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	6	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10155	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	23	78745	10100	200	10000	200	20000	80037	80136	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	0	710	1	33	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	1	3	1	21	0	0	374	69721	25	10100	100	10003	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	4	0	279	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	1	3	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	12	0	0	103	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	204	20000	80415	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	600	0	0	0	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78397	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038
10204	80037	599	0	0	0	0	0	0	61	69721	25	10100	100	10000	100	10000	500	2864300	0	80018	80037	80037	78344	0	3	78745	10100	200	10000	200	20000	80037	80037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	79677	0	10000	100	80038	80038	80038	80038	80038

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20120	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	63	61	69708	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	600	0	61	69721	25	10010	10	10000	10	10000	50	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038
10024	80037	599	0	61	69721	25	10010	10	10000	10	10000	55	2864300	1	80018	80037	80037	78366	3	78767	10010	20	10000	20	20000	80037	80037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	79677	10000	10	80038	80038	80038	80038	80038

Test 4: throughput

Count: 8

Code:

  fdiv v0.2s, v8.2s, v9.2s
  fdiv v1.2s, v8.2s, v9.2s
  fdiv v2.2s, v8.2s, v9.2s
  fdiv v3.2s, v8.2s, v9.2s
  fdiv v4.2s, v8.2s, v9.2s
  fdiv v5.2s, v8.2s, v9.2s
  fdiv v6.2s, v8.2s, v9.2s
  fdiv v7.2s, v8.2s, v9.2s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80045	600	0	0	55	25	80100	100	80000	100	80000	500	640000	1	80025	0	80044	80044	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	2	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	55	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69989	0	3	70002	80100	200	80056	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	1	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	55	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	55	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	55	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69964	0	3	70002	80100	200	80048	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	720	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	1	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	245	25	80100	100	80000	100	80000	500	640000	1	80025	0	80044	80097	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	1	0	55	25	80100	100	80000	100	80000	500	640000	0	80197	0	80044	80044	69964	0	3	70002	80100	200	80040	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	599	0	0	55	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045
80204	80044	600	0	0	55	25	80100	100	80000	100	80000	500	640000	0	80025	0	80044	80044	69964	0	3	70002	80100	200	80000	200	160000	80044	80044	1	1	80201	100	99	100	100	80000	100	0	0	0	5110	1	16	1	1	80036	80000	100	80045	80045	80045	80045	80045

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80044	600	0	1	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	6	2	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	57	0	0	0	5020	0	2	16	4	2	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	1	3	0	0	5020	0	2	16	6	2	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	6	3	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	0	0	76	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	4	3	3	80035	20	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80097	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	4	3	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	4	3	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	2	16	4	3	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80044	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	0	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	6	3	3	80035	0	80000	10	80045	80045	80045	80045	80045
80024	80097	599	0	0	0	60	25	80010	10	80000	10	80000	50	640000	1	80025	0	80044	80044	69986	3	3	70024	80010	20	80000	20	160000	80044	80044	1	1	80021	10	9	10	10	80000	10	0	0	0	0	5020	0	3	16	4	3	3	80035	0	80000	10	80045	80045	80045	80045	80045

FDIV (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations