Firestorm: FDIV (vector, 8H) measurements

Code:

  fdiv v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	7037	53	0	76	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	12	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	6	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	3	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	3	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	52	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	96	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	52	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	0	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	61	5757	25	1004	1000	1000	246258	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	5	0	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038
1004	7037	53	0	61	5757	25	1000	1000	1000	245957	7018	7037	7037	6543	3	6895	1000	1000	2000	7037	7037	1	1	1001	1000	0	3	73	1	16	1	1	6726	1000	7038	7038	7038	7038	7038

Test 2: Latency 1->2

Code:

  fdiv v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70037	524	0	33	0	232	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	12	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	726	59757	25	10100	100	10000	100	10000	500	2504957	0	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	61	59739	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	726	59757	25	10100	100	10000	108	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70084	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70037	524	408	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	42	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	42	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70084	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	30	346	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	537	61	59757	44	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	36	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70070	525	42	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	6	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	30	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	537	61	59757	25	10010	10	10000	10	10000	50	2504957	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038

Test 3: Latency 1->3

Code:

  fdiv v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70037	525	0	4	48	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	156	59757	25	10100	100	10004	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	0	84	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	4	0	0	0	726	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	525	0	0	33	0	82	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68410	3	68745	10100	202	10000	202	20000	70084	70131	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038
10204	70037	524	0	0	0	0	61	59757	25	10100	100	10000	100	10000	500	2504957	1	70018	70037	70037	68393	3	68745	10100	200	10000	200	20000	70037	70037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	69725	10000	100	70038	70038	70038	70038	70038

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70037	524	0	61	59757	25	10010	10	10000	10	10000	50	2504957	1	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	0	82	59739	25	10010	10	10000	10	10000	50	2504957	0	70018	70084	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	2	1	10021	10	9	10	10	10000	10	0	18	640	2	17	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	61	59757	25	10010	10	10000	10	10000	50	2504957	1	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70070
10024	70037	525	0	61	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	536	59739	25	10010	10	10000	10	10000	50	2504957	1	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	61	59757	25	10010	10	10000	10	10000	50	2504957	1	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	524	0	172	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	61	59757	25	10010	10	10000	10	10000	50	2504957	1	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038
10024	70037	525	0	654	59757	25	10010	10	10000	10	10000	50	2504957	0	70018	70037	70037	68415	3	68767	10010	20	10000	20	20000	70037	70037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	69726	10000	10	70038	70038	70038	70038	70038

Test 4: throughput

Count: 8

Code:

  fdiv v0.8h, v8.8h, v9.8h
  fdiv v1.8h, v8.8h, v9.8h
  fdiv v2.8h, v8.8h, v9.8h
  fdiv v3.8h, v8.8h, v9.8h
  fdiv v4.8h, v8.8h, v9.8h
  fdiv v5.8h, v8.8h, v9.8h
  fdiv v6.8h, v8.8h, v9.8h
  fdiv v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80043	600	1	0	0	87	0	305	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	6	16	1	1	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	2	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	599	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	599	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80056	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	0	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	620	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5131	1	16	1	1	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	80000	100	80044	80044	80044	80257	80044
80204	80043	599	0	1	0	0	0	54	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	80000	100	80044	80044	80044	80044	80044
80204	80043	600	0	0	0	0	0	75	25	80100	100	80000	100	80000	500	640000	80024	80043	80043	69964	3	70001	80100	200	80000	200	160000	80043	80043	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	5110	1	16	1	1	80035	80000	100	80044	80044	80044	80044	80044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80043	599	0	844	25	80010	10	80000	10	80029	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	3	0	29	16	28	28	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	182	25	80010	10	80000	10	80000	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	26	16	28	28	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	600	0	194	25	80010	10	80000	10	80000	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	28	16	14	28	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	60	626	25	80010	10	80000	10	80000	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	28	16	13	28	80036	0	0	0	80000	10	80044	80044	80044	80044	80095
80024	80043	600	0	81	25	80010	10	80000	10	80000	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	29	16	27	27	80036	2	21	19	80000	10	80044	80044	80044	80044	80044
80024	80150	599	0	257	25	80010	10	80000	10	80000	50	640000	1	80024	0	80097	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	19	16	28	28	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	600	0	226	25	80010	10	80000	10	80000	50	640000	0	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	14	16	28	14	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	184	25	80010	10	80000	10	80000	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	29	17	28	27	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	600	0	54	25	80010	10	80000	10	80000	50	640000	0	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	27	16	28	29	80036	0	0	0	80000	10	80044	80044	80044	80044	80044
80024	80043	599	0	77	25	80010	10	80000	10	80000	50	640000	1	80024	0	80043	80043	69986	3	70023	80010	20	80000	20	160000	80043	80043	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	5020	0	0	27	16	30	30	80036	0	0	0	80000	10	80044	80044	80044	80044	80044

FDIV (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations