Firestorm: FJCVTZS measurements

Code:

  fjcvtzs w0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	3	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	88	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	3	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	67	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042
2004	1041	8	0	46	25	3000	1000	2000	2000	18000	1	1022	1041	1041	745	3	774	2000	2000	2000	1041	1041	1	1	1001	1000	0	0	73	1	16	1	1	1038	1000	1000	1000	1042	1042	1042	1042	1042

Test 2: Latency 1->2 roundtrip

Code:

  fjcvtzs w0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125686	7	126241	30100	200	10002	20006	200	10002	20006	130038	130040	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	1	1	1317	0	1	16	1	1	129601	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130085	130040	125686	6	126241	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1	1	1	1318	0	1	16	0	1	129600	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126255	30100	200	10000	20000	200	10000	20000	130038	130041	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130040	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130077	130039	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	3	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130040	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129590	10000	10000	10000	10100	130039	130039	130039	130077	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130379	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	17	2	3	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	129504	25	40100	10100	20000	10000	100	20000	10000	500	5288871	9322098	0	130013	0	130038	130038	125679	3	126246	30100	200	10000	20000	200	10000	20000	130052	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	0	0	1310	1	2	16	2	2	129590	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	3	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130040
30024	130083	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	7	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130088	130039
30024	130038	974	0	0	0	9	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10047	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	2	0	0	0	1	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130040
30024	130038	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	702	0	130023	129505	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30125	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	1	0	0	4	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	2	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130058
30024	130038	974	0	5	5	0	1	130023	129508	25	40010	10011	20016	10010	11	20444	10211	55	5297334	9329272	130013	130546	130208	125706	3	126268	30010	20	10000	20000	20	10000	20000	130040	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	3	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	129504	25	40010	10010	20000	10000	10	20000	10000	50	5287724	9322098	130013	130038	130038	125701	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	0	0	1270	1	16	1	1	129590	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fjcvtzs w0, d8
  fjcvtzs w1, d8
  fjcvtzs w2, d8
  fjcvtzs w3, d8
  fjcvtzs w4, d8
  fjcvtzs w5, d8
  fjcvtzs w6, d8
  fjcvtzs w7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80057	600	0	0	12	0	34	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59993	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	0	80038	80000	80000	80100	80092	80042	80042	80042	80042
160204	80041	599	0	0	0	0	34	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59994	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	34	25	240249	80124	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59994	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5116	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	35	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59993	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	699	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59994	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	224	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59994	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5116	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	34	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59993	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	6	0	1	1	1	5117	1	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	35	25	240100	80100	160052	100	160004	500	1440024	0	80022	0	80041	80041	59976	0	7	59993	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	599	0	0	0	0	34	25	240100	80100	160000	100	160004	500	1440024	0	80022	0	80041	80041	59976	0	7	59994	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5116	0	16	0	0	80038	80000	80000	80100	80042	80042	80042	80042	80042
160204	80041	600	0	0	0	0	34	25	240100	80100	160000	100	160004	500	1440024	1	80022	0	80041	80041	59976	0	7	59994	160104	200	160016	200	160016	80041	80041	1	1	80201	100	99	100	80100	100	0	9	1	1	1	5117	0	16	1	0	80038	80000	80000	80100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80041	599	0	0	0	0	0	0	104	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80089	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	4	16	4	2	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	68	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	4	16	2	4	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	741	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	16	4	4	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	698	25	240010	80010	160000	10	160000	50	1440000	1	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	16	2	4	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	605	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	4	16	2	4	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	130	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	4	16	4	2	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	599	0	0	0	0	0	0	647	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	4	16	4	2	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	499	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	16	2	4	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	668	25	240010	80010	160000	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	4	16	6	3	80037	80000	80000	80010	80042	80042	80042	80042	80042
160024	80041	600	0	0	0	0	0	0	2140	25	240010	80010	160150	10	160000	50	1440000	0	80022	0	80041	80041	59992	3	60021	160010	20	160000	20	160000	80041	80041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	16	2	4	80037	80000	80000	80010	80042	80042	80042	80042	80042

FJCVTZS

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations