Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXNMP (scalar)

Test 1: uops

Code:

  fmaxnmp d0, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000673116111786100020382038203820382038
10042037160611686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000373116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038
100420371601561686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110002073116111786100020382038203820382038
10042037150611686251000100010002645212018203720371571318951000100020002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  fmaxnmp d0, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000014519686251010010010000100100005002847521020018200372003718421318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500041406119686251010010010000100100005002847521120018200372003718421318745101002021000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500002646119686251010010010000100100005002847521020018200372003718421318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521120018200372003718421318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820133
102042003715000006119686251010010010000100100005002847521120018200372008518425318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521020018200372003718421318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000061196862510100100100001001000050028475211200182003720037184213187451010020010000200200002003720037111020110099100100100001000000710116111979120100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521020018200372003718421318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038201812003820038
102042003715000006119686251010010010000100100005002847521020018200372003718421318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003714900008219686251010010010000100100005002847521020018200372003718421818745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150002001968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
10024200371500010091968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000111000065284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
100242003715500611968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038
1002420037150008911968625100101010000101000050284752120018020037200371844331876710010201000020200002003720037111002110910101000010000640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  fmaxnmp d0, v8.2d
  fmaxnmp d1, v8.2d
  fmaxnmp d2, v8.2d
  fmaxnmp d3, v8.2d
  fmaxnmp d4, v8.2d
  fmaxnmp d5, v8.2d
  fmaxnmp d6, v8.2d
  fmaxnmp d7, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200381500000000002925801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000002961802081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815000000000027525801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802052003815000000000027925801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000002925801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
8020420038150000000000379725801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000002950801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815000000000015925801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
802042003815000000000013825801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039
80204200381500000000004925801081008000810080020500640132120019200382003899776998980120200800322001600642003820038118020110099100100800001000000000111511801600200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200401500013425800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015516432003580000102003920039200392003920039
8002420038150003925800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000001502015416442003580000102003920039200392003920039
8002420038150003925800101080093108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015316442003580000102003920039200392003920039
8002420038150003925800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015416432003580000102003920039200392003920039
8002420038150003925800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015316342003580000102003920039200392003920039
80024200381500040025800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000300502015316432003580000102003920039200392003920039
8002420038150003925800101080065108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015416342003580000102003920039200392003920039
8002420088150006025800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015416442003580000102003920039200392003920039
8002420038150003925800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015316432003580000102003920039200392003920039
80024200381500010225800101080000108000050640000200192003820038999631001880010208000020160000200382003811800211091010800001000000502015416342003580000102003920039200392003920039