Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXNMP (vector, 4S)

Test 1: uops

Code:

  fmaxnmp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160841687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150841687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110003073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fmaxnmp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715018961196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000020007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
10204200371508161196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150661196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
10204200371501561196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000100007101161119791100001002003820038200382003820038
10204200371502461196872510100100100001001000050028476802009020037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500246119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640416221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150036119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316221978510000102003820038200382003820085
1002420037150006119687251002210100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715001829319687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200842003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fmaxnmp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037149061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038
102042003715002019196872510100100100001241000050028476801200182003720037184223187451025720010000200200002003720037111020110099100100100001000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100003640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100200640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500085119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000662847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fmaxnmp v0.4s, v8.4s, v9.4s
  fmaxnmp v1.4s, v8.4s, v9.4s
  fmaxnmp v2.4s, v8.4s, v9.4s
  fmaxnmp v3.4s, v8.4s, v9.4s
  fmaxnmp v4.4s, v8.4s, v9.4s
  fmaxnmp v5.4s, v8.4s, v9.4s
  fmaxnmp v6.4s, v8.4s, v9.4s
  fmaxnmp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102161120035800001002003920039200392003920039
80204200381500632580100100800001008000050064000012001920038200389973310023801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500364518010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010020051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102161220035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)091e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000903925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200004160004420035080000102003920039200392003920039
80024200381500048303925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200002160004220035080000102003920039200392003920039
800242003815000603925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200002160004220035080000102003920039200392003920039
80024200381500012039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100001250200004160006420035080000102003920039200392003920039
800242003815000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200006160103520035080000102003920039200392003920039
8002420038150001503925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200002160004220035080000102003920039200392003920039
8002420038150001803925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200004160002420035080000102003920039200392003920039
800242003815000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200004160004420035080000102003920039200392003920039
800242003815000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200002160002420035080000102003920039200392003920039
800242003815000903925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050200002160002420035080000102003920039200392003920039