Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXNMP (vector, 8H)

Test 1: uops

Code:

  fmaxnmp v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371606116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715012416872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fmaxnmp v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)0f1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100001000710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000001440710116111979100100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000001260710116111979100100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710116111979100100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100004000710116111979100100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000840710116111979100100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710116111979100100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000030710116111979100100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000710116111979100100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100004000710116111979100100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500340196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500145196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fmaxnmp v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715017719687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715027219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371508219687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371501061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844427187671001020100002020000200372003711100211091010100001000640216121978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fmaxnmp v0.8h, v8.8h, v9.8h
  fmaxnmp v1.8h, v8.8h, v9.8h
  fmaxnmp v2.8h, v8.8h, v9.8h
  fmaxnmp v3.8h, v8.8h, v9.8h
  fmaxnmp v4.8h, v8.8h, v9.8h
  fmaxnmp v5.8h, v8.8h, v9.8h
  fmaxnmp v6.8h, v8.8h, v9.8h
  fmaxnmp v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150120126258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051104161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010010051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150210392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000502051605520035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000502051606620035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000502041605620035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000502041605720035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000502061607620035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192011220038999631001880010208000020160000200382003811800211091010800001000000502041605520035080000102003920039200392003920039
800242003815000392580010108000010800005064000011200192003820038999631001880010208000020160000200382003811800211091010800001000000502051607620035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000502051605520035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001010000502041605420035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820087999631001880010208000020160000200382003811800211091010800001000000502051605420035080000102003920039200392003920039