Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXNM (scalar, D)

Test 1: uops

Code:

  fmaxnm d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037156116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
10042037156416872510001000100026468012018203720371572318951000100020002037203711100110000000373116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037208521100110000000073116111787100020382038203820382038
10042037166116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
10042037166116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
10042037156116872510001000100026468012018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
10042037156116872510001000100026468002018203720371572318951000100020002037203711100110000000073116111787100020382038203820382038
100420371561168725100010001000264680020182037203715723189510001000200020372037111001100000001273116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fmaxnm d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715001071968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100000157102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000207102162219791100001002003820038200382003820038
102042003715015821968725101261001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010020007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715005361968744101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000020317102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500021219687251001010100001010000502847680102001820083200841844412187671001020100002020326200372003711100211091010100001030620640416661978510000102003820038200382003820038
10024200371551512561968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001001000640616561978510000102003820038200382003820038
1002420037150001241968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640516561978510000102003820038200382003820038
10024200371500122511968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640616651978510000102003820038200382003820038
1002420037150001451968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640616651978510000102022620038201792003820038
10024200371500331471968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640616661978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640616651978510000102003820038200382003820038
1002420037149004411968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640616561978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640616651978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768010200182003720037184443187671001020100002020000200372003711100211091010100001000000640516551978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fmaxnm d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187641010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500019519687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150008419687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715004326119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000456119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216321978510000102003820038200382003820038
100242003715000053619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150002256119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000606119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006426119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640316331978510000102003820038200382003820038
10024200371500096119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715000306119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216321978510000102003820038200382003820038
100242003715000010319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100194540640216221978510000102008520084200382003820038

Test 4: throughput

Count: 8

Code:

  fmaxnm d0, d8, d9
  fmaxnm d1, d8, d9
  fmaxnm d2, d8, d9
  fmaxnm d3, d8, d9
  fmaxnm d4, d8, d9
  fmaxnm d5, d8, d9
  fmaxnm d6, d8, d9
  fmaxnm d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002008820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001003351101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381501240258010010080000100800005006400001200192003820038997331002180212200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001351101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001003951101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100016851101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973310021801002008000020016000020038200381180201100991001008000010014651101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502031611200350080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502011611200350080000102003920039200392003920039
80024200381500001342580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010006502011611200350080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010049132504511611200350080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018801182080000201600002003820038118002110910108000010003502011611200350580000102003920039200392003920039
8002420191150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010013502011611200350080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502011622200350080000102003920039200392003920039
8002420038150000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502011611200350080000102003920039200392003920039
8002420038150000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010030502011611200350080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100583502011611200350080000102003920039200392003920039