Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXNM (vector, 4S)

Test 1: uops

Code:

  fmaxnm v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000000673116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000020073116111787100020382038203820382038
10042037150082168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820862038
10042037160061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fmaxnm v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
1020420037150007261968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
102042003715000611968744101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100710116111979121100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
1020420037150001561968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
102042003715090611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038
102042003715000821968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150110026819687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100644121611919785010000102003820038200382003820038
10024200371501100268196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006441116111119785010000102003820038200382003820038
10024200371501100268196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006441116111119785010000102003820038200382003820038
1002420037150110026819687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100644131671119785010000102003820038200382003820038
1002420037150110026819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100644111661119785010000102003820038200382003820038
10024200371501100268196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006441216131119785010000102003820038200382003820038
1002420037150110026819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100644111611919785010000102003820038200382003820038
10024200371501100211219687441001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100644111661119785010000102003820038200382003820038
10024200371501100268196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001006441116111219785010000102003820038200382003820038
10024200371501100268196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006441116111219816010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fmaxnm v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150027061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382008620038
102042003715000054819687821012912310000116101525532847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200842003718422318760101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003714900053619687251010010010000100100005002847680120018200372003718422318745102562001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006405162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100036402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fmaxnm v0.4s, v8.4s, v9.4s
  fmaxnm v1.4s, v8.4s, v9.4s
  fmaxnm v2.4s, v8.4s, v9.4s
  fmaxnm v3.4s, v8.4s, v9.4s
  fmaxnm v4.4s, v8.4s, v9.4s
  fmaxnm v5.4s, v8.4s, v9.4s
  fmaxnm v6.4s, v8.4s, v9.4s
  fmaxnm v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000516731611200350800001002003920039200392003920039
802042003815010192402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
80204200381500057402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815000177402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
802042003815000249402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002008920088200392003920039
80204200381500005152580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481509392580010108000010800005064000002001902003820038999631001880010208000020160000200382003811800211091010800001000502013169112003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001902003820038999631001880010208000020160000200382003811800211091010800001000502071612122003580000102003920039200392003920039
80024200381500395880010118000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000502061610142003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001902003820038999631001880010208000020160000200382003811800211091010800001000502011161082003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001902003820038999631001880010208000020160000200382003811800211091010800001000502091611112003580000102003920039200392003920039
8002420038150151262580010108000010800005064000002001902003820038999631001880010208000020160000200382008811800211091010800001000502011166122003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000502091612102003580000102003920039200392003920039
80024200381500394880010108000010800005064000002001902003820038999631001880010208000020160000200382003811800211091010800001000502011161182003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000502091610112003580000102003920039200392003920039
80024200381500392580010108000010800005064000012001902003820038999631001880010208000020160000200382003811800211091010800001000502010167122003580000102003920039200392003920039