Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXV (8H)

Test 1: uops

Code:

  fmaxv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037226125472510001000100039816030183037303724143289510001000100030373037111001100000073216112629100030383038303830383038
100430372325125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037236125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037236125472510001000100039816030183037303724143289510001000100030373037111001100024073116112629100030383038303830383038
10043037236125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037226125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037236125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037236125472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372215325472510001000100039816030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
100430372315625472510001000100039816030183037303724143289510001000100030373037111001100020373116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fmaxv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000006129520251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100003712307101161129633100001003003830038300383003830038
102043003722501000061295472510142100100001001000050042771600300183003730037282643287451010020010000200106643003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
102043003722600000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000007101161129633100001003003830038300383003830038
1020430037225000000124295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037211020110099100100100001002223557507551161129633100001003003830038300383003830038
10204300372250003301760612954725101001001000010010000546427851203001830131301342826832874510100200100002001000030037300371110201100991001001000010000215707101161129633100001003003830038300383003830038
102043013222511000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000002007101161129633100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000003007101161129633100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000003007101161129633100001003003830038300383003830038
102043003722500000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000307101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000000277295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000001448295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
10024300372250000210166295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006405162229629010000103003830038300383003830038
1002430037225000000522295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
1002430037225000000526295472510010101000010101505042771603001830037300372828632876710010201000020100003003730037111002110910101000010004006402162229629010000103003830038300383003830038
10024300372250000564061295472510010101000010100005042771603001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fmaxv h0, v8.8h
  fmaxv h1, v8.8h
  fmaxv h2, v8.8h
  fmaxv h3, v8.8h
  fmaxv h4, v8.8h
  fmaxv h5, v8.8h
  fmaxv h6, v8.8h
  fmaxv h7, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151182161120036800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
802042003915011000089925801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220099200391180201100991001008000010001311151181161120036800001002004020040200402004020040
802042003915011000089825801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501100005125801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010006311151181171120036800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040
80204200391501100003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151181161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115007882580090108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
800242003915608222580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200391500100025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010021005020116112003680000102004020040200402004020040
800242003915003202580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
800242003915004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000050201161232003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150010992580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
800242003915009842580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039150010742580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200391500402580010108000010800005064000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040