Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAX (vector, 4S)

Test 1: uops

Code:

  fmax v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073216111787100020382038203820382038
10042037151261168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371511461168725100010001000264680020182037208415728191410001000200020732037211001100012199073116111787100020382038203820382038
1004203716061168725100010121000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203715982168725100010001000264680020182037203715723189510001000200020372037111001100000373116111787100020382038203820382038
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fmax v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820132200382003820086
102042003715000016619687251010010010000100100005002847680020018200372003718422318745101002021016620020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000018719687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372008311102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715010186119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000010319687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000021019687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204202271500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000020819687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219805010000102003820038200382003820038
10024200371500000821968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100016402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000001451968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000006311968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fmax v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100171011611197910100001002003820038200382003820038
10204200371500012419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119674251010010010000100100005002847680020054200852003718422318745101002001000020020000200372003711102011009910010010000100073311611197910100001002003820038200382003820038
1020420037150106119687251010010010000100100005002847680020018200372003718422318780101002001000020020000200372003711102011009910010010000100073211611197910100001002008520089200382003820038
10204200371500044819687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500010319687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500126119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500014519687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640716331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
100242003715000103196872510010101000010100005028476801201622003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fmax v0.4s, v8.4s, v9.4s
  fmax v1.4s, v8.4s, v9.4s
  fmax v2.4s, v8.4s, v9.4s
  fmax v3.4s, v8.4s, v9.4s
  fmax v4.4s, v8.4s, v9.4s
  fmax v5.4s, v8.4s, v9.4s
  fmax v6.4s, v8.4s, v9.4s
  fmax v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001001051102161120035800001002003920039200392003920039
8020420038150124025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161320035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680212200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
80204200381503364025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815004525801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101166120035800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000502002166520035080000102003920039200392003920039
8002420038150003925800101080000108000050640000112001920038200389996310018800102080000201600002003820038118002110910108000010000502005165620035080000102003920039200392003920039
8002420038150003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010060502002162320035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001001230502002163320035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001001470502002162320035080000102003920039200392003920039
8002420038150103925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000502005162320035080000102003920039200392003920039
8002420038150003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000502002163320035080000102003920039200392003920039
800242003815000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001001320502005163220035080000102003920039200392003920039
8002420038150003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000502003163520035080000102003920039200392003920039
8002420038150003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000502003163320035080000102003920039200392003920039