Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMINNMP (vector, 4H)

Test 1: uops

Code:

  fminnmp v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001012100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371566116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110001673116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fminnmp v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476801200182003720037184223187451057620010000204200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715029161196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150306408196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451025420010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006403162219785010000102003820038200382003820038
1002420037150000375611968725100101010000101000050284768012001820037200371844481880510010201000020200002003720037111002110910101000010000006402162219785110000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
1002420037150000234611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371490000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fminnmp v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150661196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037149061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500425196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100104100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037149061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371503816119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219837010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010106402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431882210010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420084150025119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010006402162219785110000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710161201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fminnmp v0.4h, v8.4h, v9.4h
  fminnmp v1.4h, v8.4h, v9.4h
  fminnmp v2.4h, v8.4h, v9.4h
  fminnmp v3.4h, v8.4h, v9.4h
  fminnmp v4.4h, v8.4h, v9.4h
  fminnmp v5.4h, v8.4h, v9.4h
  fminnmp v6.4h, v8.4h, v9.4h
  fminnmp v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815004025801001008000010080000500640000200192003820038998839996801002008000020016000020038200381180201100991001008000010000036511021611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000006511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500822580202122800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000016511011611200350800001002003920039200392003920039
8020420189150040258010010080000100800005006407762001920038200389973399968010020080000200160000200382003811802011009910010080000100001155110116112003519800001002003920039200392003920039
802042003815004722580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000003511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000006511011611200350800001002003920039200392003920039
802042003815024402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050202163320035080000102008720039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050202163220035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001009050203163320035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050203162320035080000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100138050202163220035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000250203163320035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010012050203163320035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996731001880010208000020160000200382003811800211091010800001000050203162320035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050203163320035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001009050203163320035080000102003920136200922009620039