Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMINNMP (vector, 4S)

Test 1: uops

Code:

  fminnmp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110005073116111787100020382038203820382038
1004203715246116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fminnmp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371503876119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150012619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150053619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715096119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371502736119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715066119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150216119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000090611968744100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000001491968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000150611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000150611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000150611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003714900060611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000360611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000150611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000150611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fminnmp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150016806119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500150886119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715002106119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500606119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640516331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
100242003715702466119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200852003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fminnmp v0.4s, v8.4s, v9.4s
  fminnmp v1.4s, v8.4s, v9.4s
  fminnmp v2.4s, v8.4s, v9.4s
  fminnmp v3.4s, v8.4s, v9.4s
  fminnmp v4.4s, v8.4s, v9.4s
  fminnmp v5.4s, v8.4s, v9.4s
  fminnmp v6.4s, v8.4s, v9.4s
  fminnmp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051102161120035800001002003920039200392003920039
80204200381500000402580100122800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000200051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039
80204200381500300402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100220000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039
802042003815000150402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502000051625200350080000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502000041642200350080000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001010502000041642200350080000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001010502000041642200350080000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001010502000041642200350080000102003920039200392003920039
80024200381500031392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502000021624200350080000102003920039200392003920039
80024200381490000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001010502000021624200350080000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001010502000021624200350080000102003920039200392003920039
80024200381490000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502000041624200350080000102003920039200392003920039
80024200381500000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502000031624200350080000102003920039200392003920039