Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMINNM (scalar, D)

Test 1: uops

Code:

  fminnm d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037153611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042085150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fminnm d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150001471968725101001001000010010000500284768012001802003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018020037200371842203187451010020010000200200002003720037111020110099100100100001000520071001161119791100001002003820038200382003820038
1020420037150004361968725101001001000010010000500284768012001802003720037184220318745101002001000020020000200372003711102011009910010010000100020071001161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001802003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
10204200371500132821968725101381001000010010000500284768002006502003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100013071001161119791100001002003820085200382003820038
1020420037150001491968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
1020420037150004991968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
102042003715000821968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038
1020420037150001701968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100000071001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500003421968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500007161968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500001071968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500002601968743100251110000101000050284768012005420037200371844431876710010201000020203382003720037111002110910101000010000199300640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
10024200371500005961968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000020640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fminnm d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000328196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715001061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000269196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000124196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000985196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002207101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000170196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715000082196872510116100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715003801968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715001681968725100101010000141000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001051006402162219785010000102003820038200382003820038
100242003715001451968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150399611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000101006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fminnm d0, d8, d9
  fminnm d1, d8, d9
  fminnm d2, d8, d9
  fminnm d3, d8, d9
  fminnm d4, d8, d9
  fminnm d5, d8, d9
  fminnm d6, d8, d9
  fminnm d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102161120035800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
8020420038150010004202580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161220035800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100001051101161120035800001002003920039200392003920039
80204200921501001588612580202100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000351102162120035800001002003920140200392014220096
8020420100150000007052580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150018825800101080000108000050640000102001932003820038999631001880010208000020160000200382003811800211091010800001000502050516442003516780000102003920039200392003920039
80024200381500392580010108000010800005064000015200190200382003899963100188001020800002016000020038200381180021109101080000100050205031635200350080000102003920039200392003920039
80024200381500392580010108000010800005064000015200190200382003899963100188001020800002016000020038200381180021109101080000100050205061644200350080000102003920039200392003920039
800242003815002292580010108000010800005064000005200190200382003899963100188001020800002016000020038200381180022109101080000100050200141676200350080000102003920039200392003920039
80024200381500392580010108000010800005064000010200190200382003899963100188001020800002016000020038200381180021109101080000100050205031669200350080000102003920039200392003920039
800242003815009852580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000100050205041643200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000100050200041644200350080000102003920039200392003920039
80024200381500612580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000100050200031647200350080000102003920039200392003920039
80024200381500392580010108000010800005064000005200190200382003899963100188001020800002016000020038200381180021109101080000100050200161653200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200190200382003899963100188001020800002016000020038200381180021109101080000100050200041667200350080000102003920039200392003920039