Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMINNM (vector, 8H)

Test 1: uops

Code:

  fminnm v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037151061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715012961168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
100420371617561168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037151061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
100420371501261168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100073116221785100020382038203820382038
100420371503361168725100010001000264680120182037203715723189510001000200020372037111001100073316111787100020382038203820382038
1004203715116561168725100010001000264680120182037203715723189510001000200020372037111001100073316111785100020382038203820382038
100420371514261168725100010001000264680020182037203715723189510001000200020372037111001100073216111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fminnm v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150010519687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150030119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006403163219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000240611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000120611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000120611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000001807261968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382008520038
1002420037150000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844403187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fminnm v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150246119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150186119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102021009910010010000100007101161119791100001002003820038200382003820038
102042003715096119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003714906119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715066119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037149000611968725100121210000121000060284768002001820037200371844431876710012201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500030611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444221876710012201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500006311968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402165519787010000102003820038200382003820038
100242003715000405611968725100101210000101000050284768002001820037200371844431876710012201000020200002003720037111002110910101000010006402161219785010000102003820038200382003820038
10024200371500027611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006422162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fminnm v0.8h, v8.8h, v9.8h
  fminnm v1.8h, v8.8h, v9.8h
  fminnm v2.8h, v8.8h, v9.8h
  fminnm v3.8h, v8.8h, v9.8h
  fminnm v4.8h, v8.8h, v9.8h
  fminnm v5.8h, v8.8h, v9.8h
  fminnm v6.8h, v8.8h, v9.8h
  fminnm v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051102161120035800001002003920039200392003920039
8020420038150102404025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
8020420038150000017025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500063042025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161220035800001002003920039200392003920039
802042003815000004025801001008000011280000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000351101161120035800001002003920039200392003920039
8020420038150002404025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001002000051101161220035800001002003920039200392003920039
8020420038149001204025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815014703925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216432003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200382180021109101080000100005020416322003580000102009120039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216332003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
80024200381500032425800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
80024200381502403925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020416112003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039
80024200381501503925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020316222003580000102003920039200392003920039
800242003815015070425800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216222003580000102003920039200392003920039