Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMINP (vector, 4S)

Test 1: uops

Code:

  fminp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716810310516872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150008216872510001000100026468002018203720371572318951000100020002037203711100110000673216221787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371533006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150006116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
10042037160006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
10042037160006116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  fminp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000061196872510125100100001251000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001004371011611197910100001002003820038200382003820038
1020420037150000444061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071221611197910100001002003820038200382003820038
10204200371500120061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001001371011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000626284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010027071011611197910100001002003820038200382003820038
102042003715000001611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010022371011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476800200652003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010012071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071211611197910100001002003820038200382003820038
102042003715000000631196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000062628476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200862003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)0f18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150002000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010300640216221978510000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010600640216221978510000102003820038200382003820038
10024200371500000006311968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010800640216221978510000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010200640216221978510000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500000009121968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010200640216221978510000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010400640216221978510000102003820038200382003820038
10024200371500000005361968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010300640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fminp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715001061968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715001561968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371490611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200872003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715003881968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010037101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150010319687251001010100001010000502847680120018020037200371844431876710010201000020203602003720037111002110910101000010006406165619785010000102003820038200382003820038
1002420037150040719687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010106406166519785010000102003820038200382003820038
1002420037150038219687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010106406166519785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006404166619785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006405164619785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006705165519785010000102003820038200382003820038
10024200371500103196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000105106406165619785010000102003820038200382003820038
1002420037150096619687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010006406165619785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010006406166519785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010006405165619785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fminp v0.4s, v8.4s, v9.4s
  fminp v1.4s, v8.4s, v9.4s
  fminp v2.4s, v8.4s, v9.4s
  fminp v3.4s, v8.4s, v9.4s
  fminp v4.4s, v8.4s, v9.4s
  fminp v5.4s, v8.4s, v9.4s
  fminp v6.4s, v8.4s, v9.4s
  fminp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102231611200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102011611200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102011611200350800001002008820039200392003920039
8020420038150000000126258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102211611200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102211611200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102211611200350800001002003920039200392003920039
8020420038150000000128258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102011611200350800001002003920039200392003920039
8020420038150000000420258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102011611200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000050000051102011611200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001220019200382003899733999680100200800002001600002003820038118020110099100100800001000000000051102211611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfl1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000085258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502001916181820035080000102003920039200392003920039
8002420038149000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502001916171620035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001020019200382003899963100188001020800002016000020038200381180021109101080000100000502001916201720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502001916182020035080000102003920039200392003920039
8002420038150000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502001816171820035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000502011716171920035080000102003920039200392003920039
8002420038150000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100032507902449232420235380000102029320188201402024220296
8002420188152110962258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502002016211820035080000102003920039200392003920039
80024200381500000263258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502001816191820035080000102003920039200392003920039
8002420038150000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000502011616171820035080000102003920039200392003920039