Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMINP (vector, 8H)

Test 1: uops

Code:

  fminp v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715015616872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715025116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715012016872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  fminp v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007103161119791100001002003820038200382003820038
102042003715003141968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007502161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371500611968725101271001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371500821968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371520611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007102171119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715001531968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500841968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371506611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500841968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fminp v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150120124196752510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715090726196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000021057101161119791100001002003820038200382003820038
10204200371503061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371506061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715012061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371506061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001001207101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010037007101161119791100001002003820038200382003820038
102042003714939061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500084196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000002706119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
1002420037150000003926425119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000006419687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
1002420037150000003085219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000004306119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fminp v0.8h, v8.8h, v9.8h
  fminp v1.8h, v8.8h, v9.8h
  fminp v2.8h, v8.8h, v9.8h
  fminp v3.8h, v8.8h, v9.8h
  fminp v4.8h, v8.8h, v9.8h
  fminp v5.8h, v8.8h, v9.8h
  fminp v6.8h, v8.8h, v9.8h
  fminp v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500012402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500021402580100100800001008000050064000002001920038200389973399968010020080000200160000201122003821802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010010551101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)a9acc2cfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500939258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020003160043200350080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020003160023200350080000102003920039200392003920039
800242003815000102258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020004160034200350080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020005160044200350080000102003920039200392003920039
8002420038150027381258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001002005020003160044200350080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020005160055200350080000102003920039200392003920039
80024200381500088258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020003160055200350080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020004160033200350080000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000005020004160033200350080000102003920039200392003920039
8002420038150025839258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001010005020005160055200350080000102003920039200392003920039