Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMIN (vector, 2S)

Test 1: uops

Code:

  fmin v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371508216872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715010316872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037208311100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  fmin v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197911100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100030071011611197910100001002003820038200382003820038
1020420037150006119687451014010410000100100005002847680020018200372003718426318745101002001000020020000200372003711102011009910010010000100000073211611197910100001002003820038200382003820038
10204200371500063119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200842003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100100071011611197910100001002003820038200382003820038
102042003715001086119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037149001261968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000661316221978510000102003820038200382003820038
100242003715009611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000300640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715000142519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
100242003715010611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010001300640216221978510000102003820038200382003820038
1002420037150002291968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010200000640216221978510000102003820038200382003820038
1002420037150009951968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010002000640216221978510000102003820038200382003820038
100242003715000611968725100101010000121015250284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038
1002420037150001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  fmin v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715096119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500254196872510100100100001001000050028476800200182003720037184222418745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150018919687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100130071011611197910100001002003820038200382003820038
1020420037150010919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000171011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500023319687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500025419687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500074719687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500016619687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000108819687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150008219687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
10024200371500022919687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150008219687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  fmin v0.2s, v8.2s, v9.2s
  fmin v1.2s, v8.2s, v9.2s
  fmin v2.2s, v8.2s, v9.2s
  fmin v3.2s, v8.2s, v9.2s
  fmin v4.2s, v8.2s, v9.2s
  fmin v5.2s, v8.2s, v9.2s
  fmin v6.2s, v8.2s, v9.2s
  fmin v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051104161120035800001002003920039200392003920039
8020420038150045258010010080187100800005006400000200192003820038997303999680100200800002001601922009020095118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001001051101161120035800001002004920039200392003920039
8020420038150940258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000651101161120035800001002003920039200392003920039
8020420038150082258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)d9ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500000081258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000305020008160151220035080000102003920039200392003920039
800242003815000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000009050200014160131320035080000102003920039200392003920039
800242003815000000590258001010800001080000506400000120019200382003899963100188001020800002016000020038200381180021109101080000100010471050200011160131020035880000102009020089200392003920039
8002420038150000003572580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000050200015160131020035080000102003920039200392003920039
80024200381500000010225800101080000108000050640000002005720038200389996310098800102080000201600002003820038118002110910108000010200012050200014160101420188080000102003920039200392003920039
800242003815000021081638001010800001180000506400000120019200382003899963100188001020800002016077820038200381180021109101080000100000305020001016091420035080000102003920039200392003920039
80024200381500000062258001010800001080000506400001120019200382003899963100188001020800002016000020038200381180021109101080000100000005020009160171420035080000102003920039200392003920039
8002420038150000003192580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000100050200013160161320035080000102003920039200392003920039
800242003815000000812580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000000050200015160171320035080000102003920039200392003920039
800242003815000000602580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000103050200011160121620035080000102003920039200392003920039