Firestorm: FMLAL2 (vector, 4S) measurements

Code:

  fmlal2 v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	36	145	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	9	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4069
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	39	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmlal2 v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	331	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	4	16	2	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	346	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	1	61	39407	25	10100	100	10000	104	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30516	40037	40037	1	1	10201	100	99	100	100	10000	100	1	3	4	0	710	1	2	16	2	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40086
10204	40037	301	2	1	138	0	61	39407	44	10100	102	10000	104	10148	500	5709700	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	710	1	2	16	2	3	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	9	0	804	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38789	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	3	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	3	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	3	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmlal2 v0.4s, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40179	40037	1	1	10201	100	99	100	100	10000	100	0	6	0	710	1	16	1	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	536	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40180	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	536	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40228	1	1	10021	10	9	10	10	10000	10	0	0	0	640	6	16	2	2	39473	10000	10	40038	40038	40038	40085	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40086	40085	40038	40086	40038
10024	40037	299	1	2	0	61	39407	25	10010	10	10000	10	10000	50	5709700	40018	40037	40037	38135	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	3	0	0	682	2	32	6	4	39593	10000	10	40038	40038	40038	40084	40038
10024	40037	300	0	0	54	61	39389	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	9	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40225	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmlal2 v0.4s, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	712	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	28	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	216	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	4	0	21	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	3	0	0	61	39380	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	208	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10444	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	6	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	12	0	124	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38144	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39677	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40131	40037	1	1	10021	10	9	10	10	10000	10	2	2	0	0	640	2	16	3	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	1	2	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	103	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	0	9	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38786	10010	20	10809	20	30000	40037	40180	1	1	10021	10	9	10	10	10000	10	0	1	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlal2 v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  fmlal2 v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  fmlal2 v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  fmlal2 v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  fmlal2 v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  fmlal2 v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  fmlal2 v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  fmlal2 v7.4s, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20078	150	1	0	1	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20046	20065	20065	6	12	80128	200	80028	200	240084	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10122	0	0	0	11	16	1	0	0	9	9	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	0	1	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	0	20046	20065	20065	6	12	80128	200	80028	200	240084	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	1	1	1	10126	0	0	0	9	16	0	0	0	7	8	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10120	3	0	0	9	16	0	0	1	10	9	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	12	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20077	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10120	0	0	0	5	16	0	0	0	10	11	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	0	266	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10115	0	0	0	10	16	0	1	0	10	11	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20147	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10115	0	0	0	10	16	0	0	0	5	10	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	0	0	0	40	25	80124	100	80000	100	80000	500	640000	0	20059	20065	20065	3	23	80100	200	80000	200	240000	20065	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10119	0	0	0	9	16	0	0	0	10	10	20062	0	0	0	160000	100	20066	20066	20066	20079	20066
160204	20065	150	0	0	0	0	0	0	21	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10120	0	0	0	10	16	0	1	1	10	11	20062	0	0	0	160000	100	20079	20078	20079	20079	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20078	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	0	0	0	0	10119	0	1	0	10	16	0	0	0	9	8	20062	0	0	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10120	0	0	0	9	16	0	0	0	10	5	20062	0	0	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20097	151	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	6	2	2	4	34	4	2	2	3	3	20058	2	40	2	160000	10	20062	20053	20062	20062	20053
160024	20061	150	0	0	0	0	74	29	80012	12	80000	12	80000	62	640000	1	1	20033	20061	20052	3	23	80012	20	80326	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10026	3	1	1	3	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	1	0	0	0	67	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10026	3	1	1	3	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	178	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10026	3	1	1	4	25	2	1	1	2	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10026	3	1	1	2	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10026	3	1	1	3	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	1	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20218	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	3	1	1	2	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	1	10026	6	1	2	2	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	151	0	0	0	0	46	29	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	3	1	1	3	25	2	1	1	4	3	20049	2	20	1	160000	10	20053	20062	20053	20053	20053
160024	20061	150	0	0	0	0	146	27	80012	12	80000	12	80000	62	640000	1	1	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	10026	3	2	1	3	25	2	1	1	3	3	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 12

Code:

  fmlal2 v0.4s, v12.4h, v13.4h
  fmlal2 v1.4s, v12.4h, v13.4h
  fmlal2 v2.4s, v12.4h, v13.4h
  fmlal2 v3.4s, v12.4h, v13.4h
  fmlal2 v4.4s, v12.4h, v13.4h
  fmlal2 v5.4s, v12.4h, v13.4h
  fmlal2 v6.4s, v12.4h, v13.4h
  fmlal2 v7.4s, v12.4h, v13.4h
  fmlal2 v8.4s, v12.4h, v13.4h
  fmlal2 v9.4s, v12.4h, v13.4h
  fmlal2 v10.4s, v12.4h, v13.4h
  fmlal2 v11.4s, v12.4h, v13.4h

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	299	0	61	9961	25	120100	100	120000	100	120000	500	5851993	1	41667	0	41688	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41687	40040	41687
120204	41686	300	0	61	9961	25	120100	100	120000	100	120000	500	5851993	1	41667	0	41686	40039	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	120000	100	41692	40040	41692	40040	41687
120204	41691	300	0	61	9961	25	120100	100	120000	100	120000	500	5851993	0	41495	0	41686	40039	24932	3	24997	120100	200	120000	200	360000	41691	41691	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41677	120000	100	40040	41687	40040	41687	41687
120204	41686	300	0	61	35689	25	120100	100	120000	100	120000	500	5851993	0	40020	0	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	120000	100	40040	41687	40040	41687	40040
120204	41701	312	0	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	41686	26577	3	24997	120100	200	120000	200	360000	40039	41688	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41692	41687	40040
120204	40039	312	3	61	35689	25	120103	100	120003	100	120000	500	5630640	1	40020	0	40039	41686	26577	3	26644	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	120000	100	40040	41687	40040	41687	40040
120204	40089	318	0	61	35689	25	120101	100	120003	100	120000	500	5630640	1	40020	0	40039	41686	26577	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41677	120000	100	40040	41692	40040	41692	40040
120204	40039	312	1	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	0	40039	41686	26577	3	26644	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41677	120000	100	41687	40040	41687	40040	41687
120204	41686	299	0	61	37966	25	120103	100	120003	100	120000	500	5630640	1	41667	0	41686	40039	24932	3	24997	120100	200	120000	200	360000	41686	40089	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41687	40040	41692
120204	41686	300	3	61	9961	25	120103	100	120003	100	120000	500	5630640	0	40020	3	41688	40039	24932	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	7610	1	16	1	1	41677	120000	100	40040	41687	40040	41687	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	6	0	0	7524	6	2	1	3	16	2	1	1	2	3	40030	15	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120003	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	42	0	0	7522	3	1	1	3	16	2	1	1	3	3	40030	15	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	120	0	0	7550	3	1	1	3	16	2	1	1	3	3	40030	15	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120000	10	120000	65	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	42	0	0	7522	3	1	1	3	16	2	1	1	2	3	40030	15	17	4	120000	10	40040	40040	40040	40040	40040
120024	41691	300	0	0	0	0	732	9961	47	120010	10	120000	13	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	1	3	24	2	1	1	3	3	40030	15	9	4	120000	10	40040	40040	40148	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120002	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	1	3	16	2	1	1	3	2	40030	15	9	4	120000	10	40040	42471	40040	40040	40040
120024	40039	300	0	0	12	0	67	9961	25	120010	10	120003	10	120000	50	5630640	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	1	3	0	0	7522	3	1	1	4	16	2	1	1	3	3	40030	15	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	171	0	67	24024	66	120175	10	120000	10	120196	50	5630640	2	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	1	120	0	0	7522	3	1	1	3	16	2	1	1	3	3	40030	15	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	109	9961	25	120010	10	120000	10	120000	50	5653032	1	1	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	9	0	0	7522	3	1	1	3	16	2	1	1	3	3	40030	15	9	4	120000	10	41692	40040	40040	40040	40040
120024	41691	300	0	0	9	1	67	37966	25	120010	10	120003	10	120000	50	5630640	1	1	40020	41691	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	6	0	0	7522	3	1	1	3	16	2	1	1	3	3	40030	15	9	4	120000	10	40040	40040	40040	40040	40040

FMLAL2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations