Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMLAL (by element, 2S)

Test 1: uops

Code:

  fmlal v0.2s, v1.2h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004403731006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
1004403730006134072510001000100053190814018403740373258338951000100030004037403711100110007073116113473100040384038403840384038
1004403730006134072510001000100053190804018403740373258338951000100030004037403711100110003073116113473100040384038403840384038
1004403730006134072510001000100053190814018403740373258338951000100030004037403711100110008373116113473100040384038403840384038
1004403730006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
10044037300456134072510001000100053190804018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
1004403730196134072510001000100053190804018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
10044037310015634072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
1004403730006134072510001000100053190814018403740373258338951000100030004037403711100110000073116113473100040384038403840384038
1004403730006134072510001000100053190804018403740373258338951000100030004037403711100110000073116113473100040384038403840384038

Test 2: Latency 1->1

Code:

  fmlal v0.2s, v1.2h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710021622394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690814001804003740037381460338745101002001000020030000400374003711102011009910010010000100000710121622394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710121622394790100001004003840038400384003840038
102044003730000005363940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710121622394790100001004003840038400384003840038
10204400372990000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710121622394790100001004003840038400384003840038
10204401803010001613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710121622395510100001004003840038400384003840038
10204400373000000613940736101001001000010010000500570690804001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710121622394790100001004003840038400384003840038
10204400843000000613940725101001001000010010000500570690814001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710131622394790100001004003840038400384003840038
10204400373000000613940725101001001000010010000500570690804001804003740037381080338745101002001000020030000400704003711102011009910010010000100000710121622394790100001004003840038400384003840038
10204400372990000613940725101001001000010010000500570690814001804003740037381080338745101002001000020030000400374003711102011009910010010000100000710121622394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100244003730000015613940725100101010000101000050570690814001804003740037381303387671001020101632030000400374003711100211091010100001001000640216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001804003740037381303387671001020100002030960400374003711100211091010100001001000663216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400373000009613940725100101010000101000050570690814001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400372990000613940725100101010000101000050570690804001804003740037381303387671001020100002030483400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038
10024400373000000613940725100101010000101000050570690804001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038
100244003729900007263940725100101010000101000050570690804001804003740037381303387671001020100002030000400374003711100211091010100001000000640216223947310000104003840038400384003840038

Test 3: Latency 1->2

Code:

  fmlal v0.2s, v0.2h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204400373000897394072510100100100001111014850057083040400180400374003738108338745101002001000020030000400374003711102011009910010010000100006630071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400180400374003738108338745101002001000020030000400374003711102011009910010010000100006130071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108338745101002001000020030000400374003711102011009910010010000100006500071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108338745101002001016720030000400374003711102011009910010010000100005730071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069081400180400374003738108338745101002001000020430000400374003711102011009910010010000100006060071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069081400180400374003738108338745101002001000020030000400374003711102011009910010010000100007230071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069081400183400374003738108338745101002001000020030000400374003711102011009910010010000100004230071011611394790100001004003840038400384003840038
1020440037299061394072510100100100001001000050057069080400180400374003738108338766101002001000020030000400374003711102011009910010010000100004130071011611394790100001004003840038400384003840038
10204400373000105394072510100100100001281010150057069081400530400374003738108338745101002001000020030000400374003711102011009910010010000100006690071011611394790100001004003840038400384003840038
1020440037300061394072510100100100001001000050057069080400180400374003738108338745101002001000020030000400374003711102011009910010010000100006500071011611394790100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037299000006139407251001013100001010000505706908140018040037400373813033876710010201000020300004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908140018040037400373813033876710010201000020300004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000020640216223947310000104003840038400384003840038
1002440037300000006139407361001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000010640216223947310000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000200640216223947310000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000000640216223947310000104003840038400384003840038
1002440037300000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000030640216223947310000104003840038400384003840038
1002440037299000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000010640216223947310000104003840038400384003840038
1002440037299000006139407251001010100001010000505706908040018040037400373813033876710010201000020300004003740037111002110910101000010000050640216223954710000104003840038400384003840038

Test 4: Latency 1->3

Code:

  fmlal v0.2s, v1.2h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
1020440037299000072639407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161039479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730010006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003729900006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003729900008239407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038
102044003730000006139407251010010010000100100005005706908040018400374003738108338745101002001000020030000400374003711102011009910010010000100007101161139479100001004003840038400384003840038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000000613940725100121010000101000050570690804001840037400373813033876710010201000020300004003740037111002110910101000010000016402162239473210000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162339475210000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006424162139473210000104003840038400384003840038
1002440037299000000613940725100101010000101000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020300004003740037111002110910101000010000006424162239473010000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690804001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000000613940725100101210000121000050570690814001840037400373813033876710010201000020300004003740037111002110910101000010000006402162239473010000104003840038400384003840038
1002440037300000000613940725100101010000101000050570690814001840037400373813033876710012201000020300004003740037111002110910101000010000006672162239473010000104003840038400384003840038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlal v0.2s, v8.2h, v9.h[1]
  movi v1.16b, 0
  fmlal v1.2s, v8.2h, v9.h[1]
  movi v2.16b, 0
  fmlal v2.2s, v8.2h, v9.h[1]
  movi v3.16b, 0
  fmlal v3.2s, v8.2h, v9.h[1]
  movi v4.16b, 0
  fmlal v4.2s, v8.2h, v9.h[1]
  movi v5.16b, 0
  fmlal v5.2s, v8.2h, v9.h[1]
  movi v6.16b, 0
  fmlal v6.2s, v8.2h, v9.h[1]
  movi v7.16b, 0
  fmlal v7.2s, v8.2h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420076150300300000585258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000000010127141614152006201600001002006620066200662006620066
160204200651503003000003442258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100000000010125121616132006201600001002006620066200662006620066
16020420065150400400000350258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100000023010127131613132006201600001002006620066200662006620066
16020420065150300300000475258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000000010127151614132006201600001002006620066200662006620066
16020420065150300300000468258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100000000010128141613132006201600001002006620066200662006620066
16020420065150500300000462258010010080000100800005006400000200462006520065323801002008000020024000020065200651116020110099100100160000100000023010128141612152006201600001002006620066200662006620066
160204200651503003000004543258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000000010125151614132006201600001002006620066200662006620066
16020420065150200300000356258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000010010128141614152006201600001002006620066200662006620066
160204200651503005000004682580100100800001008000050064000012004620065200653458022720080000200240000200652006511160201100991001001600001000000403010128141614142006201600001002006620066200662006620066
16020420065150300300000468258010010080000100800005006400001200462006520065323801002008000020024000020065200651116020110099100100160000100000003010128141615122006201600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006315000522780012128000012800006264000011020033200522005232380012208000020240000200522006111160021109101016000010000001004882126252112627200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000011020033200522005232380012208000020240000200522005211160021109101016000010002001004834126252111327200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000010520099200522005232380012208000020240000200522005211160021109101016000010220301004584126252112632200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010000001004884226252112628200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010000001004884226252111327200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010000001004884126252111327200492201160000102005320053200532005320053
1600242005215000882780012128000012800006264000011520033200522005232380012208000020240000200612005211160021109101016000010002001004884111252112211200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010000001004884125252111227200492201160000102005320053200532005320053
1600242005215000462780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010000001003384110252112513200492201160000102005320053200532005320055
1600242005215000462780012128000012800006264000011520033200522005232380012208000020240000200522005211160021109101016000010001001003586110252112513200492201160000102005320053200532005320053

Test 6: throughput

Count: 12

Code:

  fmlal v0.2s, v12.2h, v13.h[1]
  fmlal v1.2s, v12.2h, v13.h[1]
  fmlal v2.2s, v12.2h, v13.h[1]
  fmlal v3.2s, v12.2h, v13.h[1]
  fmlal v4.2s, v12.2h, v13.h[1]
  fmlal v5.2s, v12.2h, v13.h[1]
  fmlal v6.2s, v12.2h, v13.h[1]
  fmlal v7.2s, v12.2h, v13.h[1]
  fmlal v8.2s, v12.2h, v13.h[1]
  fmlal v9.2s, v12.2h, v13.h[1]
  fmlal v10.2s, v12.2h, v13.h[1]
  fmlal v11.2s, v12.2h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)031e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6069interrupt pending (6c)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
12020440039313006137059251201001001200001001200005005630640140020040039416912658232499712010020012000020036000040039416911112020110099100100120000100000761011611416831200001004004040040400404004040040
1202044003931200619961251201001001200001001200005005851869041667040039400392657732664512010020012000020036000040039416861112020110099100100120000100000761011621400301200001004004040040400404004041687
12020441691300006137966251201011001200011001200005005630640140020040039416862658232664912010020012000020036000041691400391112020110099100100120000100000761011611416771200001004004041692400404169240040
12020440039300006137966251201031001200011001200005005630640140020040039400392493232664412010020012000020036000041686400391112020110099100100120000100000761011611400301200001004168740040416924004041687
12020441691299006135689251201011001200031001200005005630640140020040039400392493232560712010020012000020036000041687400391112020110099100100120000100000761011611400301200001004004040040400404004041687
12020441686300006135689251201011001200011001200005005630640140020040039416912658232499712010020012000020036000041691400391112020110099100100120000100000761011611400301200001004004040040400404004041692
12020441686299016135689251201011001200011001200005005630640140020040039416862658232499712010020012000020036000041691400391112020110099100100120000100000761011611400301200001004004040040416924004041687
120204416863000072637966251201011001200011001200005005630640140020040039400392493232499712010020012000020036000040039400391112020110099100100120000100000761011611400301200001004169240040416924004041692
1202044169130001619961251201001001200001001200005005851869141672041691400392493232499712010020012000020036000041686400391112020110099100100120000100000761011611400301200001004004040040416924004041692
1202044169129900619961251201001001200001001200005005851869141672041691400392493232499712010020012000020036000040039416911112020110099100100120000100000761011611400301200001004168740040400404004041692

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

retire uop (01)cycle (02)0318191e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cdcfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
12002441673312000021499612512001010120000101200005056306401154002040039400392495532501912001020120000203600004003940039111200211091010120000100000007522821416412874003046177120000104004040040400404004040040
120024400392990000197899612512001110120000101200005056306400154002040039400392495532501912001020120000203600004003940039111200211091010120000100000007524821516412534003031170120000104004040040400404004041687
1200244003930000008489961251200101012000010120000505630640015400204003940039249553266661200102012000020360000400394003911120021109101012000010000000752282151621187400303194120000104004040040400404004040040
1200244003930000001819961251200101012000010120000505630640115400204168640039249553250191200102012000020360000400394003911120021109101012000010000000752282131621158400303194120000104004040040400404004040040
1200244168630000001949961251200101012000010120000505851993115400204003940039249553250191200102012000020360000400394003911120021109101012000010000000752282151621153400303194120000104004040040400404004040040
12002440039300000017799612512001010120000101200005056306401154002040039400392495532501912001020120000203600004003940039111200211091010120000100000007522821716221454003031187120000104004040040400404004040040
1200244003929900002119961251200101012000010120000505851993115400204003940039249553250191200102012000020360000400394003911120021109101012000010000000752282171621153400303194120000104004040040400404004040040
1200244168630000001779961251200101012000010120000505851869115400204003941691249553250191200102012000020360000400394003911120021109101012000010000000752282131621199400303194120000104004040040400404004040040
1200244003929900001729961251200101012000010120000505630640115400204003940039266003250191200102012000020360000400394003911120021109101012000010000000752282151621135400303194120000104004040040400404004040040
12002440039300000010729961251200101012000010120000505630640115400204003940039266043250191200102012000020360000400394003911120021109101012000010000000752282191621245416833190120000104004040040400404004040040