Firestorm: FMLAL (by element, 2S) measurements

Code:

  fmlal v0.2s, v1.2h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	7	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	3	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	8	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	45	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	1	9	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	156	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmlal v0.2s, v1.2h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38146	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	536	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40180	301	0	0	0	1	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39551	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	36	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40084	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40070	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	15	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10163	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30960	40037	40037	1	1	10021	10	9	10	10	10000	10	0	1	0	0	0	663	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	9	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30483	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmlal v0.2s, v0.2h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	897	39407	25	10100	100	10000	111	10148	500	5708304	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	66	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	61	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	65	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10167	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	57	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	204	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	60	6	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	72	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	3	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	42	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38766	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	41	3	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	105	39407	25	10100	100	10000	128	10101	500	5706908	1	40053	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	66	9	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	65	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	0	0	61	39407	25	10010	13	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	36	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	5	0	640	2	16	2	2	39547	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmlal v0.2s, v1.2h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	0	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10012	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	640	2	16	2	2	39473	2	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	3	39475	2	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	4	16	2	1	39473	2	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	642	4	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	12	10000	12	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10012	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	667	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlal v0.2s, v8.2h, v9.h[1]
  movi v1.16b, 0
  fmlal v1.2s, v8.2h, v9.h[1]
  movi v2.16b, 0
  fmlal v2.2s, v8.2h, v9.h[1]
  movi v3.16b, 0
  fmlal v3.2s, v8.2h, v9.h[1]
  movi v4.16b, 0
  fmlal v4.2s, v8.2h, v9.h[1]
  movi v5.16b, 0
  fmlal v5.2s, v8.2h, v9.h[1]
  movi v6.16b, 0
  fmlal v6.2s, v8.2h, v9.h[1]
  movi v7.16b, 0
  fmlal v7.2s, v8.2h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20076	150	3	0	0	3	0	0	0	0	0	5	85	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10127	14	16	14	15	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	0	0	3	0	0	0	0	0	3	442	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10125	12	16	16	13	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	4	0	0	4	0	0	0	0	0	3	50	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	3	0	10127	13	16	13	13	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	0	0	3	0	0	0	0	0	4	75	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10127	15	16	14	13	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	0	0	3	0	0	0	0	0	4	68	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10128	14	16	13	13	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	5	0	0	3	0	0	0	0	0	4	62	25	80100	100	80000	100	80000	500	640000	0	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	3	0	10128	14	16	12	15	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	0	0	3	0	0	0	0	0	4	543	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	10125	15	16	14	13	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	2	0	0	3	0	0	0	0	0	3	56	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	10128	14	16	14	15	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	0	0	5	0	0	0	0	0	4	68	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	45	80227	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	40	3	0	10128	14	16	14	14	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	3	0	0	3	0	0	0	0	0	4	68	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	10128	14	16	15	12	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20063	150	0	0	52	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10048	8	2	1	26	25	2	1	1	26	27	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	0	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	2	0	0	10048	3	4	1	26	25	2	1	1	13	27	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	0	5	20099	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	2	2	0	3	0	10045	8	4	1	26	25	2	1	1	26	32	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10048	8	4	2	26	25	2	1	1	26	28	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10048	8	4	2	26	25	2	1	1	13	27	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10048	8	4	1	26	25	2	1	1	13	27	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	88	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20061	20052	1	1	160021	10	9	10	10	160000	10	0	0	2	0	0	10048	8	4	1	11	25	2	1	1	22	11	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10048	8	4	1	25	25	2	1	1	12	27	20049	2	20	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	8	4	1	10	25	2	1	1	25	13	20049	2	20	1	160000	10	20053	20053	20053	20053	20055
160024	20052	150	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	3	23	80012	20	80000	20	240000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	10035	8	6	1	10	25	2	1	1	25	13	20049	2	20	1	160000	10	20053	20053	20053	20053	20053

Test 6: throughput

Count: 12

Code:

  fmlal v0.2s, v12.2h, v13.h[1]
  fmlal v1.2s, v12.2h, v13.h[1]
  fmlal v2.2s, v12.2h, v13.h[1]
  fmlal v3.2s, v12.2h, v13.h[1]
  fmlal v4.2s, v12.2h, v13.h[1]
  fmlal v5.2s, v12.2h, v13.h[1]
  fmlal v6.2s, v12.2h, v13.h[1]
  fmlal v7.2s, v12.2h, v13.h[1]
  fmlal v8.2s, v12.2h, v13.h[1]
  fmlal v9.2s, v12.2h, v13.h[1]
  fmlal v10.2s, v12.2h, v13.h[1]
  fmlal v11.2s, v12.2h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	interrupt pending (6c)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	313	0	0	61	37059	25	120100	100	120000	100	120000	500	5630640	1	40020	0	40039	41691	26582	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	41683	120000	100	40040	40040	40040	40040	40040
120204	40039	312	0	0	61	9961	25	120100	100	120000	100	120000	500	5851869	0	41667	0	40039	40039	26577	3	26645	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	2	1	40030	120000	100	40040	40040	40040	40040	41687
120204	41691	300	0	0	61	37966	25	120101	100	120001	100	120000	500	5630640	1	40020	0	40039	41686	26582	3	26649	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	41677	120000	100	40040	41692	40040	41692	40040
120204	40039	300	0	0	61	37966	25	120103	100	120001	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41692	40040	41687
120204	41691	299	0	0	61	35689	25	120101	100	120003	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	25607	120100	200	120000	200	360000	41687	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	41687
120204	41686	300	0	0	61	35689	25	120101	100	120001	100	120000	500	5630640	1	40020	0	40039	41691	26582	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	40040	40040	41692
120204	41686	299	0	1	61	35689	25	120101	100	120001	100	120000	500	5630640	1	40020	0	40039	41686	26582	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	41692	40040	41687
120204	41686	300	0	0	726	37966	25	120101	100	120001	100	120000	500	5630640	1	40020	0	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	41692	40040	41692	40040	41692
120204	41691	300	0	1	61	9961	25	120100	100	120000	100	120000	500	5851869	1	41672	0	41691	40039	24932	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	40040	40040	41692	40040	41692
120204	41691	299	0	0	61	9961	25	120100	100	120000	100	120000	500	5851869	1	41672	0	41691	40039	24932	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	40040	40040	41692

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	41673	312	0	0	0	0	214	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	4	16	4	1	2	8	7	40030	46	17	7	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	1978	9961	25	120011	10	120000	10	120000	50	5630640	0	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7524	8	2	1	5	16	4	1	2	5	3	40030	31	17	0	120000	10	40040	40040	40040	40040	41687
120024	40039	300	0	0	0	0	848	9961	25	120010	10	120000	10	120000	50	5630640	0	1	5	40020	40039	40039	24955	3	26666	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	5	16	2	1	1	8	7	40030	31	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	181	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	41686	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	3	16	2	1	1	5	8	40030	31	9	4	120000	10	40040	40040	40040	40040	40040
120024	41686	300	0	0	0	0	194	9961	25	120010	10	120000	10	120000	50	5851993	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	5	16	2	1	1	5	3	40030	31	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	177	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	7	16	2	2	1	4	5	40030	31	18	7	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	211	9961	25	120010	10	120000	10	120000	50	5851993	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	7	16	2	1	1	5	3	40030	31	9	4	120000	10	40040	40040	40040	40040	40040
120024	41686	300	0	0	0	0	177	9961	25	120010	10	120000	10	120000	50	5851869	1	1	5	40020	40039	41691	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	3	16	2	1	1	9	9	40030	31	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	172	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	40039	40039	26600	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	5	16	2	1	1	3	5	40030	31	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	1072	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	40039	40039	26604	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	7522	8	2	1	9	16	2	1	2	4	5	41683	31	9	0	120000	10	40040	40040	40040	40040	40040

FMLAL (by element, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations