Firestorm: FMLAL (vector, 4S) measurements

Code:

  fmlal v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	9	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1002	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	6	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	2	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmlal v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5708046	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39389	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	103	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	2	2	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	7	16	6	8	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	9	16	8	8	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	7	16	6	8	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	10	16	8	6	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	2	63	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	7	16	8	7	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	11	16	8	8	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	1	0	0	1	1	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	8	16	10	9	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	2	64	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	1	0	0	642	10	16	10	9	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	644	8	16	9	10	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	1	0	0	1	0	0	0	0	0	1	63	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	642	10	16	10	9	39473	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmlal v0.4s, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	0	1935	39407	25	10125	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	211	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	2	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	1	0	0	0	0	0	115	39407	25	10150	100	10000	125	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40227	40037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	213	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40086	40086	40038
10204	40037	299	0	0	0	0	0	0	103	39407	25	10129	123	10006	125	10000	500	5706908	1	40018	40037	40037	38111	6	38745	10100	200	10000	200	30000	40169	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	9	0	710	1	16	8	8	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	2	147	39389	25	10100	100	10000	125	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40231	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	61	39407	25	10100	100	10000	125	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	3	16	8	1	39479	0	10000	100	40038	40038	40038	40180	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	125	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	714	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	125	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	710	4	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	125	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	10864	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	3	0	0	61	39407	25	10100	100	10000	123	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	2	3	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	69	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	8	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	81	1	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	15	61	39407	25	10010	12	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	81	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	11	10148	50	5706908	0	40018	40037	40226	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	6	0	640	2	16	2	2	39473	0	10000	10	40120	40085	40038	40038	40038
10024	40037	300	0	0	0	0	962	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30966	40085	40037	1	1	10021	10	9	10	10	10000	10	0	0	57	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	78	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	251	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38825	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	0	81	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	57	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	61	39407	43	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	20	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	72	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmlal v0.4s, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	50	6	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40084	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	18	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	72	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	9	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	54	9	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	53	3	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40229	300	0	0	61	39407	25	10122	106	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	55	0	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	480	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	50	3	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	156	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	50	3	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	310	0	6	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	53	3	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	55	3	0	710	1	16	1	1	39479	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38155	3	38767	10010	20	10178	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40229
10024	40084	300	0	0	0	0	0	61	39407	45	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	310	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40225
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmlal v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  fmlal v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  fmlal v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  fmlal v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  fmlal v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  fmlal v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  fmlal v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  fmlal v7.4s, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	61	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	2	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	82	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20130	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	126	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	63	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	1	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	61	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	61	25	80100	100	80000	100	80000	500	640000	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20057	150	0	115	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	3	2	1	10	20	2	1	1	9	13	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	46	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	3	1	1	9	20	2	1	1	9	8	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	46	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	3	1	1	12	20	2	1	1	9	7	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	415	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	3	1	1	11	20	2	1	1	6	13	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	69	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20051	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10031	3	1	1	6	20	2	1	1	7	10	20044	2	30	160000	10	20048	20048	20048	20048	20048
160024	20047	150	57	52	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	3	1	1	6	20	2	1	1	8	12	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	92	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	1	0	0	10032	3	1	1	6	20	2	1	1	7	11	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	172	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	2	0	0	10032	3	1	1	9	20	2	1	1	13	12	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	151	0	46	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	3	1	1	9	20	2	1	1	6	12	20044	2	15	160000	10	20048	20048	20048	20048	20048
160024	20047	150	0	67	25	80012	12	80000	12	80000	62	640000	1	1	0	20028	0	20047	20047	3	23	80012	20	80000	20	240000	20047	20047	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	3	1	1	9	20	2	1	1	9	13	20044	2	15	160000	10	20048	20048	20048	20048	20048

Test 6: throughput

Count: 12

Code:

  fmlal v0.4s, v12.4h, v13.4h
  fmlal v1.4s, v12.4h, v13.4h
  fmlal v2.4s, v12.4h, v13.4h
  fmlal v3.4s, v12.4h, v13.4h
  fmlal v4.4s, v12.4h, v13.4h
  fmlal v5.4s, v12.4h, v13.4h
  fmlal v6.4s, v12.4h, v13.4h
  fmlal v7.4s, v12.4h, v13.4h
  fmlal v8.4s, v12.4h, v13.4h
  fmlal v9.4s, v12.4h, v13.4h
  fmlal v10.4s, v12.4h, v13.4h
  fmlal v11.4s, v12.4h, v13.4h

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3474

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	41685	300	0	0	726	40274	25	120103	100	120003	100	120000	500	5630640	0	41667	41686	40039	27359	3	24997	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	3	16	3	1	41683	120000	100	41692	40040	40040	40040	40040
120204	41691	312	0	0	84	9961	25	120100	100	120000	100	120000	500	5630640	0	41667	41686	40039	24932	3	24997	120100	200	120000	200	360000	41686	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	3	2	41677	120000	100	41687	40040	40040	41692	41692
120204	41686	299	0	0	61	35689	25	120103	100	120003	100	120000	500	5630640	1	41672	40039	41691	26582	3	26649	120100	200	120000	200	360000	41691	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	3	16	2	3	41677	120000	100	41687	40040	41687	41692	41687
120204	41686	300	0	3	61	35689	25	120101	100	120001	100	120000	500	5851869	1	40020	40039	41691	26577	3	26644	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	3	3	41677	120000	100	41687	40040	41687	40040	41687
120204	41691	299	0	3	61	9961	25	120100	100	120000	100	120000	500	5851869	1	40020	40039	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	3	40030	120000	100	40040	41687	40040	41689	40040
120204	40039	312	0	0	82	35689	25	120101	100	120001	100	120000	500	5851993	0	41672	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	2	0	0	0	7610	3	16	3	3	41683	120000	100	40040	41687	40040	41687	40040
120204	40039	300	9	3	94	9961	25	120100	100	120000	100	120000	500	5851869	1	41667	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	3	16	3	3	40030	120000	100	41692	40040	41692	40040	40040
120204	40039	307	0	3	61	9961	25	120103	100	120001	100	120000	500	5851869	1	41672	41686	40039	24932	3	24997	120100	200	120000	200	360000	41691	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	3	16	3	3	41677	120000	100	40040	40040	40040	41687	40040
120204	40039	312	0	3	61	9961	25	120100	100	120000	100	120000	500	5630640	0	40020	40039	40039	24932	3	24997	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	3	16	2	3	41683	120000	100	41687	40040	41692	40040	41687
120204	41686	300	0	3	66	9961	25	120100	100	120000	100	120000	500	5851993	0	41667	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	3	16	2	5	41677	120000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	300	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5851869	1	0	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	12	1	15	16	1	1	1	13	9	40030	16	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	0	40039	40039	27382	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	12	1	11	16	1	1	2	14	11	40030	15	9	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	0	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	12	0	9	16	2	1	1	15	14	40030	16	9	7	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	1	67	9961	25	120010	10	120000	10	120000	50	5966386	1	0	40020	0	40039	40039	24955	0	3	27450	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7524	3	1	12	0	16	16	2	1	1	20	14	40030	16	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	73	9961	25	120010	10	120000	10	120000	50	5630640	1	0	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	14	1	14	16	2	1	1	13	13	40030	15	9	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	0	40039	40039	26600	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	15	0	13	16	2	2	1	11	15	40030	15	9	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	4706	9961	25	120010	10	120000	10	120000	50	5630640	0	0	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	16	0	10	16	1	1	1	13	13	40030	16	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	1	0	0	0	7522	3	1	14	1	10	16	1	1	2	14	14	40030	15	17	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	73	35689	25	120010	10	120000	10	120000	50	5630640	1	1	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	7522	3	1	13	0	10	16	2	1	1	16	13	40030	16	9	4	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	732	9961	25	120010	10	120000	10	120000	50	5630640	1	0	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	3	0	7522	3	1	11	0	11	16	2	1	1	12	13	41678	15	9	4	120000	10	40040	40040	40040	40040	40040

FMLAL (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations