Firestorm: FMLA (by element, 2S) measurements

Code:

  fmla v0.2s, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	30	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	2	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	3	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	166	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	573	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4085	4085	4038	4038	4038
1004	4037	31	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla v0.2s, v1.2s, v2.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	57	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	1	1	1	717	0	2	16	0	0	39490	0	10000	100	40038	40038	40038	40038	40038
10204	40225	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38115	6	38741	10100	200	10008	200	30024	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	0	16	0	0	39489	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	408	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	566	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40230	300	0	0	0	12	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	39	0	189	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	6	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	4	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5712492	1	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	1	61	39407	25	10100	100	10000	100	10000	617	5712310	1	40018	40037	40037	38108	3	38745	10100	200	10000	212	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	3	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	299	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	3	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla v0.2s, v0.2s, v1.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	162	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	522	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	0	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	25	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	30	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	311	0	0	0	0	0	12	0	0	89	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40227	40322	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	0	0	0	640	2	16	2	2	39579	0	10000	10	40038	40038	40038	40038	40038
10024	40037	310	0	0	0	0	0	0	0	0	276	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38135	3	38787	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	1067	39407	25	10020	10	10000	10	10148	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30489	40132	40037	1	1	10021	10	9	10	10	10000	10	0	4	0	0	0	0	0	0	0	0	640	2	24	2	2	39473	0	10000	10	40038	40086	40038	40038	40038
10024	40037	310	0	0	0	0	0	0	0	0	160	39407	25	10010	12	10000	10	10296	50	5706908	0	40018	0	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	1	640	2	81	3	3	39956	4	10000	10	40606	40605	40561	40641	40606
10024	40594	304	0	0	0	12	12	1728	1232	0	6507	39308	238	10086	18	10066	17	11332	71	5719472	0	40263	0	40084	40321	38130	28	38803	10010	20	10000	20	30000	40037	40084	1	1	10022	10	9	10	10	10000	10	0	0	2	1	0	3	7	0	0	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40274	40038
10024	40037	311	0	0	0	0	2	21	0	0	907	39407	25	10017	10	10018	10	10888	50	5709700	0	40088	0	40037	40037	38130	25	38767	10160	20	10000	20	30489	40323	40037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	0	0	0	0	0	640	2	16	2	2	39691	0	10000	10	40085	40038	40178	40038	40083
10025	40037	322	0	1	0	0	0	0	0	0	203	39389	25	10010	10	10000	10	10000	60	5709700	0	40065	0	40037	40037	38130	3	38786	10160	22	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	4	1	0	0	640	2	16	1	2	39473	0	10000	10	40179	40038	40038	40038	40038
10024	40037	299	0	1	0	0	0	0	0	0	1082	39407	25	10016	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38158	3	38767	10010	20	10163	20	30972	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	0	640	2	16	2	3	39473	0	10000	10	40038	40038	40038	40038	40086

Test 4: Latency 1->3

Code:

  fmla v0.2s, v1.2s, v0.s[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	321	0	0	0	0	0	0	0	0	61	39398	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38762	10100	200	10000	200	30501	40131	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	6	0	0	0	0	710	1	16	1	1	39479	11	10000	100	40038	40038	40038	40086	40180
10204	40084	311	0	0	0	1	3	849	0	0	61	39407	25	10100	100	10018	100	10000	500	5706908	0	40018	0	40037	40084	38108	0	3	38745	10100	200	10497	200	30000	40084	40179	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	3	0	0	0	0	710	2	16	1	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	316	0	0	0	0	0	15	0	0	61	39407	83	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10557	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	0	3	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40086	40038	40038	40038	40038
10205	40037	299	0	0	0	0	0	0	88	0	1370	39407	25	10100	100	10024	100	10000	624	5706908	0	40018	0	40037	40037	38108	0	3	38745	10565	204	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	0	0	0	0	0	781	1	16	1	1	39515	0	10000	100	40038	40038	40038	40038	40087
10204	40037	318	0	0	1	1	3	375	0	0	915	39407	82	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	30000	40037	40227	1	1	10201	100	99	100	100	10000	100	2	0	2	0	0	0	10721	0	0	0	0	777	1	16	1	1	39513	0	10000	100	40038	40038	40038	40085	40132
10205	40037	300	0	0	0	0	0	0	0	0	1281	39407	25	10100	100	10000	111	10296	500	5706908	1	40018	0	40084	40037	38108	0	3	38745	10100	204	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	2	0	10679	2	0	0	0	710	1	40	1	1	39479	2	10000	100	40038	40038	40038	40172	40179
10204	40037	300	0	0	0	1	3	39	0	0	189	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38112	7	3	38764	10251	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	17	1	1	39479	0	10000	100	40038	40038	40181	40038	40181
10204	40037	300	0	0	0	0	3	0	0	0	61	39407	25	10131	100	10000	103	10000	500	5710982	0	40018	0	40037	40037	38108	0	3	38745	10100	200	10000	200	31482	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	4	9	4	0	0	0	710	1	16	1	1	39479	16	10000	100	40038	40038	40038	40217	40121
10204	40037	313	0	0	0	0	0	0	0	0	61	39407	25	10100	100	10000	100	10444	500	5706908	0	40088	0	40087	40037	38108	0	3	38745	10100	210	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	12	0	0	0	0	710	1	16	1	1	39587	0	10000	100	40038	40038	40038	40038	40086
10204	40037	311	0	0	0	0	0	867	0	0	61	39407	101	10100	100	10000	102	10444	500	5708304	0	40018	0	40037	40037	38108	0	3	38745	10266	200	10000	200	30000	40180	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	2	0	0	0	1	0	710	1	16	1	1	39585	3	10000	100	40038	40038	40038	40215	40085

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	1	0	0	0	0	0	0	0	1	82	39407	45	10018	10	10012	10	10000	50	5711096	1	40018	0	40178	40037	38130	0	3	38825	10010	20	10000	22	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	1	0	0	0	0	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	315	0	0	0	0	0	0	0	0	0	3953	39407	25	10010	10	10006	11	10000	50	5710800	0	40018	0	40037	40084	38130	0	3	38767	10010	20	10000	20	30000	40037	40085	4	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	162	0	0	0	640	0	2	16	2	6	39473	0	10000	10	40038	40038	40038	40085	40038
10024	40037	314	0	0	0	0	0	0	0	0	1	448	39407	44	10010	10	10000	12	10147	50	5706908	1	40065	0	40037	40179	38130	0	3	38767	10010	20	10000	20	30516	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	2	0	2	0	0	640	0	2	49	2	2	39473	0	10000	10	40038	40038	40227	40038	40038
10024	40037	314	0	0	0	0	0	0	0	0	0	293	39407	81	10010	10	10000	14	10000	50	5706908	1	40053	0	40083	40037	38130	0	3	38767	10310	20	10000	20	30960	40178	40037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	0	0	0	0	640	0	2	16	2	2	39473	0	10000	10	40038	40085	40038	40038	40227
10024	40037	311	0	1	0	0	0	1	153	88	0	1242	39407	25	10010	10	10018	10	10000	50	5706908	0	40018	0	40070	40037	38130	0	26	38767	10010	20	10000	20	30000	40037	40084	4	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	18	0	0	0	640	0	2	16	2	2	39547	1	10000	10	40038	40038	40038	40038	40038
10024	40037	301	0	0	0	0	3	0	0	0	0	3491	39407	84	10010	10	10000	10	10000	50	5706908	1	40018	0	40133	40037	38130	0	7	38823	10010	20	10000	22	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	2	0	0	0	0	640	0	2	16	2	2	39602	0	10000	10	40038	40038	40038	40038	40038
10024	40037	311	0	0	0	0	0	0	132	264	0	61	39407	25	10010	10	10006	10	10000	50	5706908	0	40018	0	40037	40037	38147	0	3	38767	10010	20	10000	20	30000	40085	40133	1	1	10021	10	9	10	10	10000	10	0	1	0	0	0	0	0	0	0	0	640	0	2	42	2	2	39473	0	10000	10	40038	40038	40038	40038	40086
10024	40178	317	0	0	0	0	0	1	18	264	0	61	39407	25	10010	10	10012	10	10000	50	5706908	0	40053	0	40084	40084	38152	0	3	38767	10010	20	10481	20	30486	40037	40227	1	1	10021	10	9	10	10	10000	10	4	0	2	0	0	0	10690	0	0	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	316	0	0	0	0	0	0	0	0	0	789	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	4	0	0	0	0	0	640	0	2	16	2	3	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	0	0	103	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	0	40037	40037	38130	0	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	0	0	640	0	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40085

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.2s, v8.2s, v9.s[1]
  movi v1.16b, 0
  fmla v1.2s, v8.2s, v9.s[1]
  movi v2.16b, 0
  fmla v2.2s, v8.2s, v9.s[1]
  movi v3.16b, 0
  fmla v3.2s, v8.2s, v9.s[1]
  movi v4.16b, 0
  fmla v4.2s, v8.2s, v9.s[1]
  movi v5.16b, 0
  fmla v5.2s, v8.2s, v9.s[1]
  movi v6.16b, 0
  fmla v6.2s, v8.2s, v9.s[1]
  movi v7.16b, 0
  fmla v7.2s, v8.2s, v9.s[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20074	150	0	0	0	0	0	0	0	176	0	166	25	80100	100	80000	100	80110	500	640000	0	0	20046	0	20065	20065	0	3	91	80100	200	80000	200	240000	20065	20065	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	123	0	0	0	0	10138	3	16	2	3	20062	0	160000	100	20232	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	132	264	0	302	67	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	0	3	23	80448	200	80112	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	2	0	1	0	6	0	0	0	0	10113	3	16	3	4	20062	19	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	0	40	25	80100	100	80000	100	80000	500	640896	0	0	20046	0	20065	20065	0	3	90	80236	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	15	0	0	0	0	10114	3	16	3	3	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	1	0	0	0	40	25	80100	100	80000	100	80000	500	640864	0	0	20046	0	20229	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	0	10113	3	16	2	3	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	0	105	25	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	0	3	51	80247	200	80330	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	2	0	0	0	10113	3	49	3	3	20062	17	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	0	0	0	0	61	25	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	0	10112	3	16	3	3	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	1	0	0	0	0	45	0	0	728	148	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	2	0	0	0	0	0	0	0	0	10113	3	16	4	2	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	157	1	0	0	0	0	0	0	0	0	583	25	80100	100	80000	100	80000	500	640000	0	0	20114	0	20065	20065	0	27	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	1	0	0	10113	4	16	2	5	20062	0	160000	100	20078	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	0	0	0	0	419	25	80100	100	80000	100	80000	500	640000	0	0	20046	0	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	2	0	10113	3	16	3	3	20263	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	1	0	0	0	690	25	80100	100	80000	100	80000	500	640000	0	0	20114	0	20065	20065	0	3	23	80100	200	80000	200	240000	20065	20065	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	0	10112	3	16	3	2	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20074	157	0	0	1	0	0	0	1	0	0	0	46	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20052	20052	0	3	23	80012	20	80000	20	240000	20052	20213	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10036	8	1	1	17	25	6	2	2	13	14	20049	2	20	0	1	160000	10	20053	20053	20053	20053	20053
160024	20052	150	0	0	0	0	0	0	0	0	0	0	46	27	80012	12	80000	12	80000	62	640000	0	1	5	20033	20061	20052	0	3	23	80012	20	80000	20	240000	20052	20196	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10038	11	4	2	14	34	6	1	1	12	12	20049	2	40	0	1	160000	10	20053	20053	20053	20053	20062
160024	20119	150	0	0	0	0	0	0	0	12	0	0	67	29	80012	12	80000	12	80000	62	640000	0	1	5	20042	20061	20061	0	3	23	80012	20	80000	20	240000	20061	20259	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	3	0	0	1	10039	8	5	2	13	34	8	3	1	13	8	20058	2	20	0	2	160000	10	20062	20062	20062	20053	20062
160024	20061	150	0	2	0	0	0	0	0	0	0	0	631	27	80012	12	80000	12	80000	62	640000	1	1	5	20033	20130	20061	0	3	23	80012	20	80000	20	240000	20052	20286	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10082	11	5	2	13	67	8	2	2	13	12	20194	3	40	0	2	160000	10	20053	20146	20306	20062	20053
160024	20061	150	0	0	1	0	0	0	0	3	0	0	231	29	80012	12	80000	12	80000	62	640000	0	1	5	20042	20061	20061	0	3	23	80012	20	80000	20	240000	20061	20263	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10038	11	5	2	8	34	6	14	2	14	14	20252	2	40	0	1	160000	10	20062	20053	20062	20062	20053
160024	20061	150	0	0	0	0	0	0	0	0	0	0	506	27	80012	12	80000	12	80000	62	640000	1	1	5	20042	20052	20061	0	3	23	80012	20	80000	20	240000	20052	20213	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10035	11	2	2	8	34	8	2	2	13	9	20049	2	40	0	2	160000	10	20053	20062	20053	20062	20062
160024	20061	157	0	0	0	0	0	0	0	0	88	0	352	29	80012	12	80000	12	80000	62	640000	1	1	5	20033	20303	20061	0	3	23	80012	20	80000	20	240000	20061	20271	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	2	1	0	10034	6	5	1	16	34	8	2	2	17	10	20058	2	20	0	1	160000	10	20062	20053	20053	20062	20062
160024	20061	156	0	0	0	0	0	0	0	0	0	0	178	29	80012	12	80000	12	80000	62	640000	0	1	5	20042	20061	20061	0	3	23	80012	20	80000	20	240000	20061	20516	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	6	0	0	0	10035	11	5	1	14	34	8	3	3	15	9	20058	2	40	0	2	160000	10	20143	20228	20053	20121	20053
160024	20061	156	0	0	0	0	0	0	0	0	0	0	46	29	80012	12	80000	12	80000	62	640872	0	1	5	20042	20061	20052	0	3	23	80012	20	80000	20	240000	20087	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	0	0	0	0	10037	11	5	2	14	178	4	2	2	14	12	20058	2	40	0	2	160000	10	20062	20062	20144	20312	20062
160024	20061	150	0	0	0	0	0	0	0	0	0	0	52	29	80012	12	80000	12	80000	62	640000	0	1	5	20042	20052	20061	0	3	23	80012	20	80000	20	240000	20174	20309	2	1	160021	10	9	10	10	160000	10	0	0	0	1	0	0	0	0	0	10038	11	5	2	9	224	4	2	2	14	9	20058	2	20	0	2	160000	10	20062	20062	20062	20062	20137

Test 6: throughput

Count: 12

Code:

  fmla v0.2s, v12.2s, v13.s[1]
  fmla v1.2s, v12.2s, v13.s[1]
  fmla v2.2s, v12.2s, v13.s[1]
  fmla v3.2s, v12.2s, v13.s[1]
  fmla v4.2s, v12.2s, v13.s[1]
  fmla v5.2s, v12.2s, v13.s[1]
  fmla v6.2s, v12.2s, v13.s[1]
  fmla v7.2s, v12.2s, v13.s[1]
  fmla v8.2s, v12.2s, v13.s[1]
  fmla v9.2s, v12.2s, v13.s[1]
  fmla v10.2s, v12.2s, v13.s[1]
  fmla v11.2s, v12.2s, v13.s[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3438

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40886	315	0	0	0	0	0	2	0	0	0	0	0	61	37966	50	120103	100	120003	120	120208	500	5630640	0	0	41672	0	40039	41686	26577	0	3	24997	120100	200	120000	200	360600	41284	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	18	0	0	0	7633	0	0	2	16	2	2	40030	0	120000	100	40040	40040	41692	40040	41687
120204	41686	312	0	0	0	0	0	0	0	0	0	0	0	61	14032	25	120103	100	120001	100	120000	500	5851993	0	0	40020	0	40039	41120	24932	0	3	26649	120100	200	120000	200	360672	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	9	0	3	0	0	0	7610	0	0	2	25	2	2	40030	0	120000	100	41692	40040	41687	40040	41692
120204	40109	300	0	0	0	0	0	0	0	294	0	0	0	61	9961	25	120103	100	120003	100	120000	500	5849059	0	0	41705	0	40039	41734	24932	0	3	26649	120100	200	120402	200	360000	40039	40039	1	1	120201	100	99	100	100	120000	100	2	0	0	0	4	0	0	0	0	0	7633	0	0	1	16	1	2	41709	0	120000	100	40040	41687	40040	42471	40040
120204	40089	300	0	0	1	1	0	0	0	1101	0	0	0	94	9961	25	120100	100	120000	100	120000	500	5819910	1	0	40020	0	41686	40039	24932	7	3	26649	120100	200	120000	200	360696	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	0	0	2	0	7610	0	0	2	17	2	2	40030	0	120000	100	40445	41692	41687	40040	40040
120204	40039	326	0	0	0	0	0	0	0	93	0	0	0	61	25200	25	120100	100	120000	107	120195	500	5851993	0	0	40020	0	40039	40039	25724	0	24	25002	120100	200	120000	200	360000	41686	40154	2	1	120201	100	99	100	100	120000	100	0	0	2	0	2	0	0	0	0	0	7633	0	0	2	16	2	2	40402	0	120000	100	41703	40040	40040	41692	41687
120204	41686	314	0	0	0	0	0	0	1	351	0	3	0	61	35689	25	120103	100	120001	100	120000	500	5630640	0	0	40020	3	41686	40039	26579	0	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120202	100	99	100	100	120000	100	0	0	0	0	40	0	691	0	0	0	7610	0	0	2	16	2	2	40030	0	120000	100	40040	41692	40093	41164	41687
120204	41686	300	0	0	1	0	0	0	0	126	88	3	0	61	37966	25	120103	100	120003	100	120000	500	5851869	0	0	41672	0	40039	41691	25498	0	3	26645	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	2	0	0	0	680	0	0	0	7610	0	0	2	17	2	2	40030	0	120000	100	40040	40090	42471	41687	42471
120204	41719	311	0	0	0	1	0	0	0	318	0	0	0	324	35689	25	120103	100	120003	100	120000	500	5851869	0	0	40020	0	40039	41691	24932	0	3	24997	120100	200	120000	200	360000	41686	40039	2	1	120201	100	99	100	100	120000	100	0	0	2	0	0	0	0	0	0	1	7610	0	0	2	16	2	2	40030	0	120000	100	41687	40040	41692	40040	41687
120205	40039	300	1	0	0	0	0	0	0	144	0	3	0	391	35689	25	120194	100	120054	100	120203	500	5846889	0	0	41702	3	41686	40039	24932	0	3	26649	120308	202	120000	200	360000	41686	41006	1	1	120201	100	99	100	100	120000	100	0	0	0	0	37	0	706	0	0	0	7633	0	0	2	16	2	2	41709	10	120000	100	40040	40040	40040	40040	40040
120204	40039	323	0	0	0	0	0	0	0	120	0	0	0	410	35689	47	120203	100	120000	116	120000	500	5627949	1	0	41672	0	40039	41686	24931	0	3	24997	120100	202	120000	200	360000	41721	41461	1	1	120201	100	99	100	100	120000	100	0	2	0	0	46	0	9	0	0	0	7657	0	0	2	16	2	2	40108	0	120000	100	41687	40040	41703	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	c9	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	40039	326	1	3	24	0	0	0	779	9961	86	120010	10	120000	10	120000	66	5630640	1	1	40020	0	40039	40039	26583	0	3	25039	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	2	2	6	0	0	0	0	7522	3	1	1	6	16	4	2	1	6	6	40030	0	40	10	5	120000	10	40040	40040	41775	41094	40094
120024	40039	300	1	0	12	88	0	0	73	31598	46	120010	10	120080	10	120000	55	5843165	0	1	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	5	1	120021	10	9	10	10	120000	10	0	2	0	0	0	0	0	0	7593	3	1	2	4	16	4	2	2	4	6	40552	1	40	10	0	120000	10	40040	40040	40040	40040	40040
120024	40039	324	0	0	0	0	0	0	73	9961	87	120010	10	120000	10	120000	55	5630640	1	1	40570	0	40226	40260	24955	0	3	25200	120010	20	120200	20	360000	40451	41337	1	1	120021	10	9	10	10	120000	10	2	0	0	690	0	3	0	0	7547	6	2	2	4	16	2	1	1	2	4	40030	0	20	20	0	120000	10	40040	40040	40040	40040	40282
120024	40039	308	0	0	0	352	3	0	1147	15867	25	120243	10	120000	10	120196	50	5643833	2	1	40020	0	40039	40039	24955	0	10	25019	120010	20	120000	20	360585	41182	41686	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7522	3	2	1	2	16	2	1	1	4	2	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	322	0	0	0	0	0	0	288	9961	25	120010	10	120001	10	120000	50	5630640	1	1	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	6	0	0	0	0	0	0	7522	3	1	1	6	16	2	1	1	3	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	318	0	0	9	0	0	0	267	9961	25	120069	10	120000	10	120200	50	5630640	2	1	40020	0	40039	40039	26604	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120022	10	9	10	10	120000	10	0	46	0	0	0	0	0	0	7522	3	1	1	2	16	2	1	1	4	2	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	311	0	0	30	0	0	0	67	9961	25	120011	10	120000	10	120000	50	5630640	1	1	40020	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7522	3	2	2	4	16	2	1	1	2	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	310	0	0	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	40070	0	40039	40090	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	1	7522	3	1	2	4	16	2	1	2	2	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	310	0	0	66	0	0	0	732	9961	25	120010	10	120000	10	120000	50	5626942	1	1	40020	0	40039	40039	24955	0	3	25019	120210	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7522	3	1	3	3	16	2	1	1	4	2	40030	0	40	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	310	0	0	36	0	0	1	395	9961	25	120010	10	120000	10	120000	60	5630640	1	1	40071	0	40039	40039	24955	0	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	0	7522	3	1	2	2	16	2	1	1	4	4	40030	0	20	10	5	120000	10	40040	40040	40040	40040	40040

FMLA (by element, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations