Firestorm: FMLA (by element, 4H) measurements

Code:

  fmla v0.4h, v1.4h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	4037	31	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	325	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	0	203	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	328	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	31	0	0	0	321	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	21	340	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	11	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	0	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	0	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	15	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038
1004	4037	30	0	0	0	61	3407	25	1000	1000	1000	531908	1	4018	4037	4037	3258	3	3895	1000	1000	3000	4037	4037	1	1	1001	1000	1	0	73	1	16	1	1	3473	1000	4038	4038	4038	4038	4038

Test 2: Latency 1->1

Code:

  fmla v0.4h, v1.4h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	1	0	243	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40083	40038
10204	40037	300	0	0	0	0	0	82	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40230	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	726	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	103	39407	25	10100	100	10000	100	10148	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	712	1	2	16	2	2	39479	20	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	536	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	0	0	61	39389	25	10100	100	10000	100	10000	500	5706908	40018	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	0	0	0	0	0	82	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	6	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	147	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	1	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	66	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	3	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	39473	0	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	0	0	0	0	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	39473	0	10000	10	40038	40038	40038	40038	40038

Test 3: Latency 1->2

Code:

  fmla v0.4h, v0.4h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	81	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	42	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	12	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	243	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	311	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	0	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	2	2	39479	0	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	0	87	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	42	0	76	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	33	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	117	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	471	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	87	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	42	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	36	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	0	6	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	0	252	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40065	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	39473	10000	10	40038	40038	40038	40038	40038

Test 4: Latency 1->3

Code:

  fmla v0.4h, v1.4h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	40037	300	0	0	294	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	27	0	0	156	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	39	132	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	36	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40086	40038
10204	40037	300	0	0	24	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	39	0	0	76	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	299	0	0	30	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	9	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	6	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	30	0	0	61	39407	25	10100	100	10000	100	10000	500	5706908	1	40018	0	40037	40037	38108	3	38745	10100	200	10000	200	30000	40037	40037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	39479	0	10000	100	40038	40038	40038	40038	40038
10204	40037	300	0	0	345	0	0	6976	39326	206	10196	151	10048	145	11184	772	5719396	1	40333	0	40358	40468	38138	41	38836	11477	226	11494	214	34488	40471	40467	10	1	10201	100	99	100	100	10000	100	4	0	1	2	28548	0	908	1	89	1	2	39797	36	10000	100	40038	40038	40038	40038	40038

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	40037	300	0	726	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	11	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	299	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	1	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038
10024	40037	300	0	61	39407	25	10010	10	10000	10	10000	50	5706908	0	40018	40037	40037	38130	3	38767	10010	20	10000	20	30000	40037	40037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	39473	10000	10	40038	40038	40038	40038	40038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fmla v0.4h, v8.4h, v9.h[1]
  movi v1.16b, 0
  fmla v1.4h, v8.4h, v9.h[1]
  movi v2.16b, 0
  fmla v2.4h, v8.4h, v9.h[1]
  movi v3.16b, 0
  fmla v3.4h, v8.4h, v9.h[1]
  movi v4.16b, 0
  fmla v4.4h, v8.4h, v9.h[1]
  movi v5.16b, 0
  fmla v5.4h, v8.4h, v9.h[1]
  movi v6.16b, 0
  fmla v6.4h, v8.4h, v9.h[1]
  movi v7.16b, 0
  fmla v7.4h, v8.4h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	15	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	3	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	515	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	515	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	1	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	6	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	0	16	2	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	40	25	80100	100	80000	100	80000	500	640000	1	20046	20065	20065	3	23	80100	200	80000	200	240000	20065	20065	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	0	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20061	151	0	7	0	0	46	25	80012	12	80000	12	80000	62	640000	3	1	20034	20053	20053	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10064	6	2	2	42	22	1	1	1	33	37	20046	2	31	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	2	0	0	58	25	80012	12	80000	12	80000	62	640000	3	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10061	3	1	1	34	22	1	1	1	36	24	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	1	4	381	0	58	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20053	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10058	3	1	1	36	22	1	1	1	38	39	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	4	0	0	52	25	80012	12	80000	12	80000	62	640000	3	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10062	3	1	1	38	22	1	1	1	39	39	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	3	4	0	1	52	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	2	0	0	10063	3	1	1	38	22	1	1	1	39	38	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	151	3	5	15	0	58	25	80012	12	80000	12	80000	62	640000	3	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10061	3	1	1	39	22	1	1	1	27	39	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	2	5	0	0	70	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20053	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10049	3	1	1	40	22	1	1	1	40	40	20046	2	16	160000	10	20050	20050	20054	20050	20050
160024	20049	150	3	4	0	1	70	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10060	3	1	1	38	22	1	1	1	25	40	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	150	2	6	0	1	70	25	80012	12	80000	12	80000	62	640000	3	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10063	3	1	1	27	22	1	1	1	41	28	20046	2	16	160000	10	20050	20050	20050	20050	20050
160024	20049	151	1	4	0	1	64	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	23	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10063	3	1	1	38	22	1	1	1	24	36	20046	2	16	160000	10	20050	20050	20050	20050	20050

Test 6: throughput

Count: 12

Code:

  fmla v0.4h, v12.4h, v13.h[1]
  fmla v1.4h, v12.4h, v13.h[1]
  fmla v2.4h, v12.4h, v13.h[1]
  fmla v3.4h, v12.4h, v13.h[1]
  fmla v4.4h, v12.4h, v13.h[1]
  fmla v5.4h, v12.4h, v13.h[1]
  fmla v6.4h, v12.4h, v13.h[1]
  fmla v7.4h, v12.4h, v13.h[1]
  fmla v8.4h, v12.4h, v13.h[1]
  fmla v9.4h, v12.4h, v13.h[1]
  fmla v10.4h, v12.4h, v13.h[1]
  fmla v11.4h, v12.4h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3474

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	40039	300	0	0	0	597	0	4	61	35689	25	120103	100	120003	100	120000	500	5630640	1	40020	40039	41691	26577	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	2	2	0	0	7610	1	16	1	1	40030	120000	100	40040	41687	40040	41692	40040
120204	40039	310	0	0	0	0	0	3	61	9961	25	120100	100	120000	100	120000	551	5851993	1	40020	40039	41686	26579	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	41677	120000	100	40040	40040	40040	40040	41687
120204	41686	299	0	0	0	0	0	3	61	35689	25	120100	100	120000	100	120000	500	5851993	1	40020	40190	40130	26577	3	26649	120100	200	120000	200	360000	41688	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41687	40040	41687
120204	41686	312	0	0	0	0	0	0	61	35689	25	120100	100	120000	100	120000	500	5851869	1	40020	40039	41686	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	2	0	0	0	0	0	7610	1	16	1	1	42461	120000	100	41687	40040	41687	40040	41687
120204	40039	299	0	0	0	0	0	0	61	37966	25	120101	100	120003	100	120000	500	5851993	1	40020	40039	41686	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	40030	120000	100	40040	41687	40040	40040	40040
120204	41691	300	0	0	0	0	0	0	61	35689	25	120101	100	120003	100	120000	500	5630640	1	41672	41691	40039	24932	3	24997	120100	200	120000	200	360000	40039	41691	1	1	120201	100	99	100	100	120000	100	0	0	0	0	6	0	7610	1	16	1	1	40030	120000	100	41687	40040	41687	40040	41687
120204	41688	301	0	0	4	0	0	3	61	9961	25	120100	100	120000	100	120000	500	5851993	1	40020	40039	41686	26582	3	26649	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	40030	120000	100	41687	40040	41687	40040	41687
120205	41702	300	0	0	0	0	0	1	61	9961	25	120100	100	120000	100	120000	500	5851993	1	41667	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	40030	120000	100	41692	40040	41687	40040	40040
120204	41686	299	0	0	0	0	0	0	61	9961	25	120100	100	120000	100	120000	500	5851993	1	40020	40039	41686	26577	3	26644	120100	200	120000	200	360000	41686	40039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	41683	120000	100	41692	40040	41687	40040	41687
120204	41691	299	0	0	0	0	0	1	61	37966	25	120103	100	120001	100	120000	500	5630640	1	41672	41686	40039	24932	3	24997	120100	200	120000	200	360000	40039	41686	1	1	120201	100	99	100	100	120000	100	0	0	0	0	0	0	7610	1	16	1	1	40030	120000	100	41692	40040	41692	40040	41687

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3337

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	41691	300	1	0	0	0	109	9961	25	120010	10	120000	10	120000	50	5630640	2	1	0	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	9	0	9	0	0	7522	8	4	1	17	16	2	1	1	16	5	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	2	1	5	40020	40039	40039	24955	3	27450	120010	20	120000	20	360000	40039	42470	1	1	120021	10	9	10	10	120000	10	0	0	0	0	18	0	0	7522	8	5	1	16	16	2	1	1	16	6	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	1	0	0	162	9961	25	120010	10	120000	10	120000	50	5630640	2	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	8	5	1	13	16	2	1	1	16	7	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	41686	312	0	0	33	264	67	9961	25	120010	10	120000	10	120000	50	5630640	2	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	8	5	1	5	16	2	1	1	16	7	41678	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	195	9961	25	120010	10	120000	10	120000	50	5630640	2	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	8	5	1	16	16	2	2	1	7	16	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5851869	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	1	0	0	0	7522	8	5	1	16	16	2	1	1	16	16	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	299	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	2	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	8	5	1	16	16	2	1	1	16	7	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	0	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	8	5	1	16	41	2	1	1	17	17	40030	20	10	5	120000	10	40040	40040	40040	40040	40040
120024	40039	300	0	0	21	0	67	9961	25	120010	10	120000	10	120000	50	5630640	1	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	0	0	0	7522	8	5	1	5	16	2	1	1	8	17	40030	20	10	5	120000	10	40040	40040	41696	40040	40040
120024	40039	299	0	0	12	0	67	9961	25	120010	10	120001	10	120000	50	5630640	0	1	5	40020	40039	40039	24955	3	25019	120010	20	120000	20	360000	40039	40039	1	1	120021	10	9	10	10	120000	10	0	0	0	0	27	0	0	7522	8	5	1	5	16	2	1	1	17	17	40030	20	10	5	120000	10	40040	40040	40040	40040	40040

FMLA (by element, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations